Double Side Polished Silicon Wafers 

Double Side Polished Silicon Wafer Inventory

UniversityWafer supplies double side polished (DSP) silicon wafers with a wide range of electrical, crystallographic, dimensional, and surface specifications. Available material may include Czochralski (CZ) and Float Zone (FZ) silicon, p-type and n-type material, high-resistivity silicon, multiple crystal orientations, and both standard and custom thicknesses.

The inventory below includes examples of DSP silicon with tightly controlled total thickness variation (TTV). Some configurations may also specify bow, warp, orientation tolerance, resistivity, wafer flats or notches, and other parameters important for precision fabrication.

Inventory and availability can change. When selecting a wafer, verify the complete specification rather than assuming that all DSP wafers have the same surface quality or dimensional tolerances.

Understanding the DSP Inventory Specifications

A DSP inventory table contains several specifications that should be considered together. The polishing designation describes the surface finish, while electrical, crystallographic, and geometric parameters determine whether the substrate is suitable for a particular experiment or fabrication process.

Type and Dopant

Silicon conductivity is controlled by electrically active dopants. Boron (B) is commonly used as an acceptor to produce p-type silicon, while phosphorus (P) and antimony (Sb) are donor dopants used to produce n-type silicon.

The conductivity type and dopant should be selected according to the electrical requirements of the device. They are independent of whether the wafer is SSP or DSP.

Crystal Orientation

The orientation identifies the crystallographic plane approximately parallel to the wafer surface. Common silicon wafer orientations include Si(100), Si(110), and Si(111), although specialty orientations and intentional off-axis cuts are also available.

Orientation can influence anisotropic etching, surface atomic structure, oxidation behavior, epitaxial growth, and other fabrication processes. Learn more about silicon wafer orientation.

Wafer Thickness

Wafer thickness affects mechanical stiffness, handling, device geometry, thermal behavior, and compatibility with fabrication equipment. DSP silicon is available in both conventional and specialty thicknesses.

For applications requiring substantially reduced substrate thickness, see ultra-thin silicon wafers.

Electrical Resistivity

Silicon resistivity is commonly specified in ohm-centimeters (Ω·cm) and is related to the concentration and mobility of charge carriers in the material.

Low-resistivity silicon contains a relatively high concentration of electrically active dopants and is useful when greater electrical conductivity is required. Higher-resistivity material has lower free-carrier concentration and can be advantageous for RF, microwave, detector, photonic, dielectric-isolation, and other specialized applications.

High-Resistivity FZ Double Side Polished Silicon

Float Zone (FZ) silicon is produced using a crucible-free crystal-growth process. Compared with conventional CZ silicon, FZ material generally contains substantially less oxygen and can be manufactured with very high electrical resistivity.

High-resistivity DSP FZ wafers can be useful for applications in which substrate conduction or RF loss must be minimized. Examples include microwave devices, RF structures, detectors, photonics, high-frequency characterization, and specialized sensor research.

High resistivity alone does not determine RF or photonic performance. Surface condition, interface states, oxide charge, device geometry, frequency, processing history, and other material properties can also influence substrate-related losses.

What Does Low TTV Mean?

Total Thickness Variation (TTV) describes the difference between the maximum and minimum measured thickness of a wafer under a defined measurement method and condition.

A lower TTV indicates more uniform thickness across the wafer. Tight TTV can be particularly important for precision lithography, wafer bonding, MEMS, thinning, optical processing, and applications where thickness uniformity affects the final device geometry.

Some DSP wafers can be manufactured with exceptionally tight TTV, but DSP and low TTV are not synonymous. TTV must be specified and measured independently from surface polish.

TTV, Bow and Warp Are Different Specifications

TTV, bow, and warp describe different aspects of wafer geometry and should not be used interchangeably.

• TTV describes variation in wafer thickness.
• Bow describes a global curvature-related displacement of the wafer median surface relative to a reference plane under defined measurement conditions.
• Warp describes overall deviation of the wafer median surface from a reference plane and can capture more complex wafer-shape distortion.

A wafer can therefore have very low TTV while still exhibiting measurable bow or warp. When wafer geometry is critical, specify acceptable limits for each relevant parameter.

DSP Silicon for Backside Lithography

Double-side polishing is particularly useful when both sides of the wafer participate in the fabrication process. A polished backside can facilitate backside photoresist processing, alignment, inspection, metrology, and pattern transfer.

Double-sided processing is common in selected MEMS and sensor fabrication processes where frontside structures must be aligned with backside cavities, membranes, vias, or other features.

Actual alignment accuracy is determined by the lithography equipment, alignment marks, wafer geometry, optical properties, process design, and other factors; DSP alone does not establish alignment accuracy.

DSP Silicon for Wafer Bonding

Wafer bonding can benefit from DSP substrates when the process requires controlled surfaces on both sides of the silicon wafer.

Bonding quality may depend on surface roughness, particles, contamination, flatness, bow, warp, surface chemistry, and bonding conditions. These requirements can be particularly demanding for direct wafer bonding, where intimate contact between very smooth and clean surfaces is important.

Other bonding methods, including anodic, adhesive, eutectic, and intermediate-layer bonding, have different surface and process requirements.

DSP Silicon for MEMS and Sensors

Double side polished silicon is commonly selected for MEMS and sensor processes that require fabrication from both wafer surfaces. Applications may include:

• Pressure-sensor diaphragms
• Micromachined membranes
• Accelerometers and inertial structures
• Microfluidic devices
• Resonators
• Backside cavities
• Through-wafer structures
• Wafer-level sensor packaging

Silicon is particularly useful for MEMS because its mechanical properties, crystal structure, processing chemistry, and compatibility with established semiconductor fabrication methods are well characterized.

DSP Silicon for Photonics and Optical Research

DSP silicon can also be useful in photonic and optical experiments when both substrate surfaces must have controlled finishes or when backside processing, bonding, thinning, or optical characterization is required.

Crystalline silicon is not transparent throughout the visible spectrum, but it becomes useful as an optical material over portions of the near-infrared and infrared spectrum where absorption is sufficiently low for the intended application. Exact transmission depends on wavelength, thickness, doping, temperature, and material quality.

For integrated photonic structures requiring a thin silicon device layer above an insulating layer, silicon-on-insulator (SOI) may be more appropriate than a conventional bulk DSP wafer.

DSP Silicon for Thin-Film Deposition

Double-side polished wafers provide controlled surfaces for thin-film deposition and materials research. Depending on the experiment, films may be deposited by sputtering, evaporation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other techniques.

Processing both sides can be useful for stress-compensation studies, backside coatings, optical structures, sensors, bonding layers, and other experimental architectures.

Film stress can also change wafer bow and warp after deposition, even when the starting DSP substrate has tightly controlled geometry.

CZ vs. FZ DSP Silicon Wafers

Selecting the Right Double Side Polished Silicon Wafer

The correct DSP substrate depends on the complete fabrication process. Researchers should consider more than diameter and polish when comparing wafers.

Important parameters include:

• Diameter and thickness
• CZ or FZ crystal growth
• P-type or n-type conductivity
• Dopant species
• Electrical resistivity
• Crystal orientation and orientation tolerance
• Total Thickness Variation (TTV)
• Bow and warp
• Front and backside surface roughness
• Flat or notch configuration
• Edge condition
• Quantity and intended process

Providing the intended application—such as MEMS, wafer bonding, lithography, RF, photonics, deposition, or thinning—can help identify an appropriate wafer specification.

Double Side Polished Silicon Wafers for Research

UniversityWafer supplies DSP silicon substrates for universities, laboratories, semiconductor development, MEMS, photonics, sensors, wafer bonding, thin-film research, and other precision fabrication applications.

Related Double Side Polished Silicon Wafer Resources

• Silicon Wafers – Explore silicon substrates by diameter, thickness, orientation, dopant, resistivity, and surface finish.
• Total Thickness Variation (TTV) – Learn why wafer thickness uniformity matters for lithography, bonding, MEMS, and precision fabrication.
• Prime Grade Silicon Wafers – Device-quality silicon substrates for semiconductor processing, microfabrication, MEMS, and research.
• Test Grade Silicon Wafers – Lower-cost silicon wafers for process development, equipment testing, deposition trials, and research.
• Float Zone (FZ) Silicon Wafers – Low-oxygen, high-purity silicon with high-resistivity options for RF, detectors, photonics, and specialized devices.
• High-Resistivity Silicon Wafers – Silicon substrates for applications where reduced free-carrier conduction or substrate-related electrical loss is important.
• Ultra-Thin Silicon Wafers – Thin and mechanically flexible silicon substrates for MEMS, sensors, photonics, packaging, and specialized research.
• Silicon Wafer Orientation – Compare Si(100), Si(110), Si(111), and other orientations for etching, deposition, epitaxy, and device fabrication.
• Silicon Wafer Resistivity – Understand how dopant concentration, carrier concentration, and mobility influence silicon resistivity.
• Silicon Wafers for MEMS – Explore substrates for micromachined sensors, membranes, cavities, resonators, microfluidics, and other MEMS structures.
• Wafer Bonding – Learn about substrate and surface requirements for direct, anodic, adhesive, and other wafer-bonding processes.
• Silicon-on-Insulator (SOI) Wafers – Engineered silicon substrates with a crystalline device layer separated from the handle wafer by a buried insulator.
• Thin-Film Deposition – Learn about silicon substrates for PVD, CVD, ALD, sputtering, evaporation, and functional thin-film research.