Silicon-on-Insulator (SOI) Wafers

SOI Inventory

Review sample SOI wafer inventory for silicon photonics, RF electronics, CMOS research, and MEMS sensors. Compare device-layer thickness, buried oxide (BOX) thickness, handle-wafer dimensions, and wafer diameter. The table represents sample configurations; confirm current stock, quantities, and specifications before ordering.

Understanding SOI Layer Structure

Silicon-on-Insulator wafers are engineered substrates composed of three distinct layers. Understanding this structure is key to selecting the right wafer for your application.

1. The Device Layer (Top Silicon)

The active silicon device layer is where transistors, sensors, and optical waveguides are fabricated. Its thickness is selected to match the mechanical, electrical, or optical requirements of the process.

• For Photonics: Usually 220nm or 340nm to confine light.
• For MEMS: Often 10µm to 100µm to provide mechanical mass for accelerometers.

2. The Buried Oxide (BOX) Layer

The buried oxide (BOX) layer is silicon dioxide (SiO₂) that isolates the upper silicon device layer from the handle wafer. Its thickness affects electrical isolation and, for optical sensor and photonics applications, optical confinement.

• Standard: 1µm to 3µm is common for optical isolation.
• RF-SOI: May use special "trap-rich" layers under the BOX to further improve linearity.

3. The Handle Wafer

The silicon handle wafer supports the SOI stack during fabrication. For RF device research, high-resistivity silicon can help reduce unwanted substrate-related RF losses; the appropriate handle specification depends on the device design.

SOI Wafer Manufacturing: SIMOX vs. Bonded SOI

We supply SOI wafers manufactured using the two primary industry methods:

SIMOX (Separation by Implantation of Oxygen)

SIMOX SOI wafers are produced by oxygen-ion implantation into silicon followed by thermal annealing, forming a buried oxide layer beneath the silicon surface.

• Best for: Thin-film devices, radiation-hardened electronics.

Wafer Bonding (Bonded SOI)

Bonded SOI wafers are produced by joining silicon wafers through an oxide interface and thinning the donor silicon to the required device-layer thickness. Bonded structures support a wide range of custom layer thicknesses.

• Best for: MEMS, Power devices, and applications requiring thick Device or BOX layers.

SOI Wafer Applications: MEMS, RF, CMOS and Photonics

Silicon-on-insulator substrates provide a controlled silicon device layer above an insulating oxide, making them useful across several semiconductor fabrication processes. Choose the layer thickness, BOX thickness, wafer diameter, and electrical properties around your design.

• MEMS fabrication: Thick-device-layer SOI supports accelerometers, pressure sensors, micromachined structures, and microfluidic devices.
• Silicon photonics: Thin-device-layer SOI, including 220 nm configurations, supports optical waveguides and integrated photonic structures.
• RF and microwave devices: High-resistivity handle wafers and engineered substrate options support RF switches and other high-frequency components.
• CMOS research: Thin SOI can help limit parasitic capacitance and support device isolation in integrated circuits.
• Optical sensors: SOI structures are used in integrated optics and sensing-device development.