We are developing fully depleted SOI transistors for low-power integrated circuits and require high-quality SIMOX silicon-on-insulator wafers with a thin silicon device layer, controlled buried oxide thickness, and excellent interface quality for CMOS-compatible fabrication. Can you recommend suitable substrates for our research?
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UniversityWafer supplies high-quality SIMOX (Separation by IMplantation of OXygen) silicon-on-insulator (SOI) wafers for universities, government laboratories, semiconductor manufacturers, and research institutions developing advanced electronic devices. Whether your project involves fully depleted SOI (FDSOI) transistors, RF integrated circuits, MEMS, photonic devices, or radiation-hardened electronics, we can help you find the right substrate.
Buy Online or request a custom quotation for your exact specifications, including device-layer thickness, buried oxide (BOX) thickness, wafer diameter, crystal orientation, resistivity, doping type, and surface finish.
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Why Researchers Choose SIMOX Wafers
- Excellent electrical isolation provided by the buried oxide (BOX) layer.
- Reduced parasitic capacitance for high-speed semiconductor devices.
- Supports FDSOI transistor, CMOS, RF, MEMS, and photonic device fabrication.
- Compatible with many conventional silicon processing techniques.
- Available with custom device-layer and buried oxide thicknesses.
- Offered in multiple wafer diameters, orientations, doping types, and resistivity ranges.
- Ideal for advanced semiconductor research, prototyping, and university laboratories.
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Common SIMOX Research Applications
- Fully Depleted SOI (FDSOI) transistors
- CMOS integrated circuits
- RF and microwave devices
- MEMS sensors and actuators
- Silicon photonics
- Radiation-hardened electronics
- Power semiconductor research
- Microelectronic device fabrication
- Advanced semiconductor process development
What Is a SIMOX Wafer?
A SIMOX wafer is a type of silicon-on-insulator (SOI) wafer manufactured by implanting oxygen ions beneath the surface of a silicon substrate. SIMOX stands for Separation by Implantation of Oxygen. After implantation, the wafer is annealed at a high temperature so the implanted oxygen forms a continuous buried silicon dioxide layer.
The finished substrate contains three main regions:
- Silicon device layer: The upper silicon layer used to fabricate transistors, circuits, sensors, or optical structures.
- Buried oxide layer: The electrically insulating silicon dioxide layer, commonly called the BOX layer.
- Silicon handle wafer: The supporting substrate beneath the buried oxide.
This layered structure electrically separates devices from the underlying silicon substrate. It can reduce unwanted substrate interactions and provide researchers with greater control over the electrical behavior of experimental semiconductor devices.
| SIMOX Wafer Key Takeaways | |
|---|---|
| Technology | SIMOX uses oxygen-ion implantation and high-temperature annealing to form a buried silicon dioxide layer inside a silicon wafer. |
| Structure | A thin silicon device layer sits above a buried oxide layer, which is supported by a silicon handle substrate. |
| Main Benefits | Electrical isolation, reduced parasitic capacitance, improved device control, and compatibility with silicon processing. |
| Applications | SOI transistors, radiation-tolerant electronics, RF circuits, MEMS, sensors, photonics, and integrated-circuit research. |
| Available Options | Different device-layer thicknesses, buried oxide thicknesses, wafer diameters, crystal orientations, doping types, and resistivity ranges. |
How Are SIMOX Wafers Manufactured?
SIMOX fabrication begins with a high-quality single-crystal silicon wafer. Oxygen ions are implanted below the wafer surface at a controlled energy and dose. The implantation conditions determine the approximate depth and concentration of oxygen within the silicon.
The implanted wafer is then subjected to high-temperature annealing. During this step, the oxygen reacts with silicon to form the buried silicon dioxide layer. Annealing also helps repair implantation-related crystal damage in the upper silicon device layer.
The general SIMOX process includes:
- Selecting a silicon wafer with the required orientation, doping type, and resistivity.
- Implanting oxygen ions at a carefully controlled energy and dose.
- Annealing the wafer to form a continuous buried oxide layer.
- Restoring and improving the crystalline quality of the upper silicon layer.
- Performing optional epitaxial growth, polishing, or thinning to reach the required device-layer thickness.
- Characterizing the final layer thicknesses, uniformity, surface condition, and electrical properties.
Why Use SIMOX Silicon-on-Insulator Wafers?
The buried oxide layer in a SIMOX substrate provides dielectric isolation between the active silicon device layer and the handle wafer. This can improve device performance in applications where substrate capacitance, leakage, electrical coupling, or isolation are important.
Important benefits include:
- Electrical isolation: The buried oxide helps isolate neighboring devices and reduces unwanted current paths through the substrate.
- Reduced parasitic capacitance: Lower junction and substrate capacitance can support faster switching and lower dynamic power consumption.
- Improved latch-up resistance: Dielectric isolation reduces the parasitic structures associated with latch-up in conventional bulk CMOS.
- Lower substrate coupling: SIMOX can be useful in RF, analog, and mixed-signal circuits where electrical interference must be minimized.
- Thin device layers: Controlled silicon thickness supports fully depleted transistor structures and nanoscale device research.
- Process compatibility: SIMOX wafers can be processed using many conventional silicon fabrication methods.
SIMOX Compared with Bonded SOI
SIMOX and bonded SOI wafers both contain a silicon device layer above a buried oxide layer, but they are produced differently. SIMOX creates the oxide inside a single silicon wafer through oxygen implantation. Bonded SOI is generally created by bonding oxidized silicon surfaces and transferring or thinning one of the silicon layers.
| Feature | SIMOX SOI | Bonded SOI |
|---|---|---|
| Manufacturing method | Oxygen implantation followed by high-temperature annealing | Wafer bonding and silicon layer transfer or thinning |
| Buried oxide formation | Created within the silicon wafer | Created before or during wafer bonding |
| Device-layer control | Controlled through implantation, annealing, epitaxy, and polishing | Available across a broad range through layer transfer and thinning |
| Typical research use | Implantation-based SOI studies, radiation research, RF devices, and specialized electronics | CMOS, MEMS, photonics, power devices, and general SOI fabrication |
| Selection consideration | Useful when the implantation-formed structure or a specific SIMOX process is required | Often selected when wider device-layer or BOX thickness options are needed |
The best choice depends on the desired device-layer thickness, BOX thickness, crystalline quality, thermal requirements, fabrication process, and final device architecture. UniversityWafer can help researchers compare SIMOX with other SOI wafer technologies.
SIMOX Wafer Specifications
SIMOX wafers can be supplied with different physical and electrical specifications. Researchers should define the parameters that directly affect their fabrication process and device performance.
| Specification | Research Considerations |
|---|---|
| Wafer diameter | Select a diameter compatible with the available lithography, deposition, etching, and measurement equipment. |
| Device-layer thickness | Influences depletion behavior, device geometry, optical confinement, and mechanical structures. |
| Buried oxide thickness | Affects electrical isolation, capacitance, thermal transport, and optical behavior. |
| Crystal orientation | Common options include (100), (110), and (111), depending on the device and etching process. |
| Doping type | P-type or N-type silicon may be selected according to the intended electronic structure. |
| Resistivity | Low-, standard-, or high-resistivity silicon may be required for electronic, RF, or sensor applications. |
| Surface finish | Single-side polished or double-side polished surfaces may be selected for frontside and backside processing. |
| Flatness | Bow, warp, and total thickness variation can affect lithography, bonding, and device uniformity. |
When requesting a quote, include the desired wafer diameter, device-layer thickness, buried oxide thickness, handle-wafer thickness, orientation, doping, resistivity, surface finish, and quantity.
Fully Depleted SOI Transistor Research
Thin SIMOX device layers can support research involving fully depleted silicon-on-insulator transistors. In a fully depleted device, the silicon body is thin enough for the depletion region to extend through most or all of the active layer.
This architecture can provide improved electrostatic control of the transistor channel and may reduce some short-channel and leakage effects. Researchers use thin SOI substrates to study low-power CMOS, body-biasing techniques, novel gate structures, and nanoscale transistor behavior.
Radiation-Tolerant Electronics
SIMOX wafers have been widely investigated for radiation-tolerant and radiation-hardened electronics. The buried oxide electrically separates active devices from the bulk silicon substrate, which can help reduce some radiation-induced parasitic effects.
Potential research areas include:
- Spacecraft and satellite electronics
- Particle detectors
- Nuclear instrumentation
- High-energy physics experiments
- Radiation-response characterization
- Radiation-hardened integrated circuits
Actual radiation performance depends on the device design, oxide quality, fabrication process, total ionizing dose, particle type, bias conditions, and operating environment.
RF and Microwave Applications
The electrical isolation provided by the BOX layer can reduce substrate coupling and losses in high-frequency circuits. For this reason, SIMOX and other SOI substrates are used in research involving RF and microwave electronics.
Applications can include:
- RF switches
- Low-noise amplifiers
- Oscillators and mixers
- On-chip inductors
- Coplanar waveguides
- Millimeter-wave circuits
- Wireless communication devices
Researchers should consider handle-wafer resistivity, BOX thickness, device-layer resistivity, interface quality, and parasitic conduction when selecting an SOI substrate for high-frequency applications.
SIMOX Wafers for MEMS and Sensors
The silicon device layer and buried oxide can also support MEMS device fabrication. The BOX layer can function as an electrical insulator and an etch-stop layer during micromachining.
Possible MEMS and sensor applications include:
- Pressure sensors
- Accelerometers
- Resonators
- Microheaters
- Mechanical test structures
- Microfluidic devices
- Inertial sensors
- Integrated optical sensors
Device-layer thickness is particularly important in MEMS research because it influences the dimensions, stiffness, resonant behavior, and mechanical strength of released silicon structures.
Silicon Photonics Applications
SOI substrates are widely used for silicon photonics because silicon has a significantly higher refractive index than silicon dioxide. This index contrast allows the silicon device layer to confine and guide light.
SIMOX wafers may be evaluated for research involving:
- Silicon waveguides
- Optical resonators
- Modulators
- Photonic sensors
- Integrated optical circuits
- Optoelectronic device integration
For photonics applications, researchers should carefully evaluate device-layer thickness, BOX thickness, surface roughness, thickness uniformity, absorption, and interface quality.
Power Device Research
SIMOX substrates can be used to investigate lateral power devices and electrically isolated power integrated circuits. The buried oxide helps separate the active device from the handle substrate and can simplify the integration of power and control components.
However, silicon dioxide has lower thermal conductivity than silicon. As a result, heat dissipation and self-heating must be considered when designing high-power devices on SOI substrates. Device geometry, BOX thickness, wafer thinning, thermal contacts, and packaging can all influence thermal performance.
SIMOX Wafer Characterization
Characterization is important because SIMOX device performance depends on the quality and uniformity of the device layer, buried oxide, and interfaces. Available measurements may include:
- Ellipsometry: Measures silicon and oxide layer thicknesses.
- Four-point probe testing: Measures sheet resistance or resistivity.
- Atomic force microscopy: Evaluates surface roughness.
- Secondary ion mass spectrometry: Profiles oxygen, dopants, and impurities.
- Transmission electron microscopy: Examines layer interfaces and crystal structure.
- Defect inspection: Identifies particles, crystal defects, and surface imperfections.
- Bow and warp measurements: Verify wafer geometry and processing compatibility.
The required characterization package depends on the research application and the level of specification control needed.
Processing and Handling Considerations
SIMOX wafers can be processed using many standard semiconductor techniques, but the thin device layer and buried oxide may require adjustments to established bulk-silicon processes.
- Handle wafers by the edge or use suitable vacuum handling equipment.
- Verify that cleaning chemicals are compatible with exposed silicon dioxide.
- Control thermal ramp rates during high-temperature processing.
- Account for the BOX layer when selecting implantation energies.
- Use silicon-to-oxide etch selectivity when the BOX functions as an etch stop.
- Consider self-heating when fabricating high-current or high-power devices.
- Review bonding and backside-processing requirements before selecting the handle-wafer thickness.
- Store substrates in clean wafer carriers to reduce particles and surface contamination.
How to Select a SIMOX Wafer
Before ordering a SIMOX substrate, identify the specifications that directly affect your device structure and fabrication process.
- Determine the required silicon device-layer thickness.
- Select the buried oxide thickness needed for electrical or optical isolation.
- Choose the wafer diameter supported by your fabrication equipment.
- Specify crystal orientation, doping type, and resistivity.
- Decide whether single-side or double-side polishing is required.
- Define acceptable bow, warp, thickness variation, and surface roughness.
- Identify any required analytical or electrical characterization.
- Provide the quantity and intended application when requesting a quote.
UniversityWafer supplies SIMOX silicon-on-insulator wafers and other SOI substrates for universities, research laboratories, startups, and semiconductor manufacturers. Custom and small-quantity options may be available for device development, prototyping, and specialized research.
Frequently Asked Questions About SIMOX Wafers
What does SIMOX mean?
SIMOX means Separation by Implantation of Oxygen. It describes the oxygen implantation and annealing process used to create a buried oxide layer inside a silicon wafer.
Is SIMOX the same as SOI?
SIMOX is one method of manufacturing an SOI wafer. All SIMOX wafers are SOI substrates, but not all SOI wafers are manufactured using SIMOX. Other SOI methods include wafer bonding and layer-transfer processes.
What is the buried oxide layer?
The buried oxide, or BOX, is the silicon dioxide layer located between the upper silicon device layer and the silicon handle substrate. It provides electrical and optical isolation.
What applications use SIMOX wafers?
SIMOX wafers are used in research involving fully depleted transistors, radiation-tolerant electronics, RF circuits, MEMS, sensors, integrated circuits, power devices, and silicon photonics.
Can SIMOX wafer specifications be customized?
Available customization may include device-layer thickness, BOX thickness, wafer diameter, handle-wafer thickness, crystal orientation, doping type, resistivity, and surface finish. Availability depends on the requested combination and quantity.
What information should I include in a quote request?
Include the wafer diameter, device-layer thickness, buried oxide thickness, handle thickness, orientation, doping type, resistivity, polish, quantity, application, and any required characterization data.