High-Resistivity Float Zone Silicon
- Growth method: Float Zone (FZ)
- Diameter: 6 inches
- Length: 25 mm
- Conductivity: n-type
- Dopant: Phosphorus
- Crystal orientation: <100>
- Resistivity: 7,025–7,865 Ω·cm
- Edge configuration: One SEMI flat
Request a Quote for Silicon Ingots and Wafers
UniversityWafer supplies Czochralski (CZ), Float Zone (FZ), and NTD silicon for semiconductor fabrication, MEMS, photonics, power electronics, solar research, and university laboratories. Available material may include complete silicon ingots, ingot sections, individual wafers, and partial wafer cassettes.
Tell us the required diameter, crystal orientation, conductivity type, dopant, resistivity, thickness, surface finish, and quantity. We can help identify an appropriate silicon ingot or silicon wafer for your process.
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Silicon Ingot and Wafer FAQs
What is a silicon ingot?
A silicon ingot is a cylindrical single crystal grown from high-purity silicon using a process such as Czochralski or Float Zone crystal growth. The ingot is ground to the required diameter, oriented, and sliced into thin silicon wafers for semiconductor and photovoltaic applications.
What is silicon wafer flatness?
Silicon wafer flatness describes how closely the wafer surface follows an ideal plane. Important flatness measurements include Total Thickness Variation (TTV), bow, warp, site flatness, and global flatness.
An example of an ultra-flat wafer specification is a 100 mm prime-grade, p-type, boron-doped <100> silicon wafer with:
- Thickness: 490–510 µm
- Resistivity: 0.005–0.020 Ω·cm
- Surface finish: Double-side polished
- Total Thickness Variation: Less than 1 µm
Ultra-flat silicon wafers are commonly requested for SOI fabrication, wafer bonding, MEMS, lithography, and processes requiring tight control of layer thickness.
What is the surface roughness of a silicon wafer?
Surface roughness depends on wafer grade, polish, supplier, and measurement method. Many prime-grade polished silicon wafers are supplied with a very smooth surface suitable for lithography, epitaxy, deposition, and device fabrication.
Some prime-grade wafers may have a specified surface roughness below approximately 5 Å Ra. Always confirm whether the requirement is expressed as Ra, RMS, or another roughness parameter, because these values are not interchangeable.
What is a silicon wafer?
A silicon wafer is a thin, flat substrate sliced from a monocrystalline silicon ingot. It provides the foundation on which microelectronic, photonic, MEMS, sensor, and photovoltaic devices are fabricated.
Typical wafer-processing steps include oxidation, doping, ion implantation, photolithography, thin-film deposition, etching, epitaxy, metallization, wafer bonding, dicing, and packaging.
Learn more about what a semiconductor wafer is and how wafers are used in device fabrication.
Do you sell platinum-coated silicon wafers?
Yes. Silicon wafers can be supplied with platinum and other sputtered or evaporated metal films. Available options may include adhesion layers, multilayer metal stacks, patterned coatings, or custom film thicknesses.
Include the silicon wafer diameter, conductivity, resistivity, polish, metal type, adhesion layer, film thickness, deposition method, and quantity when requesting a quotation.
Can I buy only one silicon wafer?
Yes. UniversityWafer supplies individual silicon wafers, small quantities, and partial cassettes. Single wafers are commonly purchased for university research, prototype fabrication, equipment testing, feasibility studies, and student projects.
Individual wafers can be shipped in a protective wafer carrier appropriate for the wafer diameter.
How should a silicon wafer be cleaned before oxidation?
Silicon wafers are commonly cleaned before thermal oxidation, diffusion, or chemical vapor deposition using a process based on the RCA clean. The purpose is to reduce organic contamination, particles, native oxide when appropriate, and ionic or metallic contamination.
A typical cleaning sequence may include:
- Removal of organic contamination and particles
- Optional removal of native silicon dioxide
- Removal of ionic and metallic contaminants
- Rinsing with high-purity deionized water
- Controlled drying before the next process step
The exact chemistry and sequence should be selected according to the wafer coating, device process, contamination limits, and laboratory safety procedures.
Can a 200 mm silicon wafer be resized to 100 mm?
In some cases, a 200 mm silicon wafer can be laser-cut or diced into smaller circular substrates or custom shapes. The number of usable pieces depends on kerf width, edge exclusion, flats or notches, wafer thickness, existing films, crystal orientation, and dimensional tolerances.
Resized pieces may require additional edge finishing, cleaning, or polishing depending on the final application. Send a drawing or finished dimensions for a feasibility review.
What is silicon wafer reclaim?
Silicon wafer reclaim is the process of removing existing films, residues, patterns, or surface damage so that a wafer can be cleaned, polished, inspected, and reused.
Reclaimed wafers are commonly used as monitor wafers, equipment qualification wafers, deposition substrates, handling wafers, or economical process-development material. Reclaim services can also help reduce material cost and remove proprietary device structures before disposal or reuse.
Silicon Materials for Research and Fabrication
- Ultra-thin silicon wafers for MEMS membranes, flexible devices, sensors, solar research, temporary bonding, and substrate-transfer experiments
- Thick silicon wafers for mechanical carriers, deposition substrates, fixtures, masks, microfluidics, and polymer membrane fabrication
- Intrinsic and high-resistivity silicon for RF, photonics, detectors, low-loss devices, electrical isolation, and specialized semiconductor research
- Low-resistivity silicon for conductive handles, electrodes, backside contacts, electrochemical experiments, and epitaxial reactor development
- Prime-grade silicon for lithography, epitaxy, device fabrication, oxidation, implantation, and tightly controlled semiconductor processes
- Test and mechanical-grade silicon for deposition trials, equipment setup, process development, training, and cost-sensitive research
How to Select a Silicon Wafer
The best substrate depends on the intended device and fabrication process. Consider the following specifications before ordering:
- Wafer diameter
- Crystal orientation, such as <100>, <110>, or <111>
- p-type, n-type, intrinsic, or undoped silicon
- Boron, phosphorus, arsenic, or antimony dopant
- Target resistivity or carrier concentration
- Wafer thickness and thickness tolerance
- Single-side or double-side polishing
- Surface roughness and flatness
- TTV, bow, warp, and site-flatness limits
- Thermal oxide, silicon nitride, metal, or epitaxial coatings
- Quantity, grade, and budget
Review the silicon resistivity guide and semiconductor doping information when comparing available substrates.
Silicon Ingots for Wafer Fabrication
UniversityWafer supplies silicon ingots, silicon ingot sections, and finished silicon wafers for semiconductor manufacturing, MEMS, microelectronics, photonics, power devices, photovoltaics, and university research. Available material may include Czochralski (CZ), Float Zone (FZ), and Neutron Transmutation Doped (NTD) silicon with a range of crystal orientations, dopants, resistivities, diameters, and lengths.
Silicon ingot availability changes frequently. Some pieces are suitable for slicing into wafers, while others may be used as bulk single-crystal silicon samples, process-development material, electrical test specimens, calibration samples, or research-grade silicon sections.
Available Silicon Ingot Examples
Unless specifically identified as Float Zone or another growth type, available silicon ingots may be Czochralski-grown silicon. Contact UniversityWafer to confirm current inventory and certification data.
NTD Float Zone Silicon Ingot Section
- Inventory reference: E944
- Growth and doping method: FZ, neutron transmutation doped
- Diameter: 4 inches
- Length: 50 mm
- Conductivity: n-type
- Dopant: Phosphorus
- Crystal orientation: <100>
- Resistivity: 265–336 Ω·cm
- Minority-carrier lifetime: Greater than 200 µs
- Edge configuration: One SEMI flat
- Manufacturer: PHTS
Reference the applicable inventory number when requesting specifications, photographs, dimensional tolerances, material documentation, and current pricing.
CZ vs. FZ Silicon Ingots
The silicon crystal-growth method affects oxygen content, available diameter, resistivity range, purity, radial uniformity, mechanical behavior, and suitability for specific semiconductor devices.
| Property | CZ Silicon | FZ Silicon |
|---|---|---|
| Growth Process | Crystal is pulled from molten silicon held in a crucible. | A molten zone moves through a silicon rod without a crucible. |
| Oxygen Content | Typically higher due to interaction with the quartz crucible. | Typically lower because no crucible is used during crystal growth. |
| Available Diameter | Commonly available in larger diameters. | Generally available in more limited diameters. |
| Resistivity | Available from heavily doped to moderately high resistivity. | Often selected for high- and ultra-high-resistivity requirements. |
| Common Uses | Integrated circuits, MEMS, sensors, research, and general semiconductor processing. | RF devices, power electronics, detectors, high-resistivity substrates, and specialized research. |
What Is NTD Silicon?
Neutron Transmutation Doped silicon is produced by exposing high-purity silicon to a controlled neutron flux. Some silicon atoms are transformed into electrically active phosphorus dopants, producing highly uniform n-type doping throughout the crystal.
NTD silicon may be selected for applications that require tightly controlled radial resistivity, uniform electrical properties, high-voltage performance, power semiconductor development, detectors, or specialized electronic research. Actual suitability depends on resistivity, lifetime, oxygen content, crystal defects, orientation, and the intended process.
How Silicon Ingots Become Wafers
The manufacture of silicon wafers begins with a cylindrical single-crystal silicon ingot. The ingot is characterized and then processed into wafers through a sequence that may include:
- Crystal inspection: Confirming diameter, orientation, resistivity, dopant, and crystal quality
- Diameter grinding: Producing the required ingot diameter and cylindrical geometry
- Flat or notch formation: Identifying crystal orientation and, in some cases, conductivity information
- Wire sawing: Slicing the ingot into wafers of controlled thickness
- Edge shaping: Rounding the wafer edge to reduce chipping and breakage
- Lapping or grinding: Improving thickness uniformity and removing saw damage
- Chemical etching: Removing mechanically damaged surface material
- Polishing: Producing SSP or DSP surfaces with the required roughness and flatness
- Cleaning and inspection: Removing contamination and verifying wafer quality
Finished wafers may then undergo photolithography, etching, ion implantation, diffusion, oxidation, deposition, epitaxy, wafer bonding, metallization, or device fabrication.
Silicon Wafers Available from 1 to 12 Inches
UniversityWafer supplies prime, test, monitor, reclaim, and mechanical-grade silicon wafers in diameters ranging from small research substrates to 300 mm wafers. Inventory may include undoped, lightly doped, moderately doped, heavily doped, intrinsic, and high-resistivity silicon.
Representative wafer configurations may include:
- 1-inch undoped silicon: <100>, resistivity greater than 1,000 Ω·cm, approximately 250 µm thick, DSP
- 2-inch p-type silicon: Boron-doped, <100>, 1–10 Ω·cm, approximately 280 µm thick, SSP
- 3-inch n-type silicon: Phosphorus-doped, <100>, 0.01–0.02 Ω·cm, approximately 380 µm thick, DSP
- 4-inch intrinsic or high-resistivity silicon: <100>, resistivity greater than 20,000 Ω·cm, approximately 500 µm thick, DSP
- 6-inch p-type silicon: Boron-doped, <111>, resistivity below 1 Ω·cm, approximately 300 µm thick, SSP
- 8-inch high-resistivity silicon: <100>, resistivity greater than 5,000 Ω·cm, approximately 750 µm thick, SSP
- 12-inch p-type silicon: Boron-doped, <100>, 10–20 Ω·cm, approximately 850 µm thick, DSP
These are representative specifications rather than guaranteed current inventory. Confirm availability before designing a fabrication process around a particular wafer diameter, thickness, resistivity, or surface finish.
Undoped, Low-Doped, and Highly Doped Silicon
The appropriate silicon resistivity and dopant concentration depend on how the substrate will function inside the device. UniversityWafer can help researchers select material based on electrical, optical, mechanical, and fabrication requirements.
- Undoped or intrinsic silicon: Selected when low free-carrier concentration or high electrical resistivity is important
- Lightly doped silicon: Used when controlled conductivity and relatively high resistivity are required
- Moderately doped silicon: Common for general device fabrication, test structures, MEMS, and electronic research
- Highly doped silicon: Used when the wafer must provide a conductive handle, electrode, backside contact, or low-resistance path
Review the silicon resistivity guide and doping concentration information when comparing substrate options.
Ultra-Thin Silicon Wafers and Custom Thicknesses
Ultra-thin silicon wafers are available for flexible electronics, MEMS membranes, sensors, solar research, optical components, microfluidics, temporary bonding, device transfer, and thin-substrate experiments.
Example material may include 100 mm p-type, boron-doped, <100> silicon with a resistivity of 1–10 Ω·cm and a thickness near 25 µm. Specialized silicon may be thinned further for appropriate applications, although handling, bow, breakage, surface damage, and thickness uniformity become increasingly important as the substrate becomes thinner.
Coated and Processed Silicon Wafers
Silicon wafers can be supplied with deposited or thermally grown films for semiconductor process development and device fabrication.
- Thermal oxide silicon wafers with wet- or dry-grown silicon dioxide
- Silicon nitride wafers with LPCVD, low-stress LPCVD, or PECVD films
- Silicon wafers with sputtered or evaporated metal coatings
- Silicon epitaxial wafers with controlled epi thickness and doping
- Silicon-on-insulator wafers for MEMS, photonics, RF, CMOS, and device-isolation research
Custom services may also include wafer dicing, resizing, thinning, polishing, coating, reclaim, laser cutting, and fabrication of small quantities for research and prototype development.
Small Quantities and Partial Wafer Cassettes
Researchers do not always need a full 25-wafer cassette. UniversityWafer supplies individual wafers, small quantities, partial cassettes, excess inventory, and economical test-grade material for feasibility studies, student projects, process development, and laboratory experiments.
Research Example: Silicon Substrates for a Biobattery
A senior design team requested an economical silicon substrate for a biobattery project. Their process required photolithographic patterning followed by deposition of precious-metal catalyst and conductor layers.
Important substrate considerations for this type of project include:
- Whether the silicon substrate must be electrically conductive or electrically isolated
- Compatibility with photoresist coating, exposure, development, and lift-off
- Metal adhesion and the need for titanium, chromium, or another adhesion layer
- Required wafer diameter and thickness
- Single-side or double-side polishing
- Surface roughness and cleanliness
- Whether a thermal oxide insulating layer is needed
- Compatibility with wet chemicals and biological materials
- Budget, required quantity, and allowable wafer grade
A low-cost test-grade silicon wafer may be adequate for early process development. However, a thermal oxide coated wafer may be more appropriate when the metal electrodes must be electrically isolated from the silicon substrate.
Research Example: Silicon and Germanium for EEW
A nanomaterials laboratory used a strip broken from a boron-doped silicon wafer in an electrical explosion of wires experiment. The researchers then requested a comparable germanium wafer less than 500 µm thick.
For this type of electrical experiment, relevant specifications may include bulk resistivity, conductivity type, substrate thickness, crystal orientation, mechanical strength, contact resistance, surface condition, and sample geometry. Silicon and germanium have different electrical, thermal, and mechanical properties, so the replacement material should be selected according to the required current density, pulse energy, heating behavior, and experimental objective.
Applications for Silicon Ingots and Wafers
- Integrated circuit and transistor research
- MEMS sensors and actuators
- RF and microwave devices
- Power semiconductor development
- Photodetectors and imaging devices
- Photonics and optical components
- Solar cells and photovoltaic research
- Thin-film deposition and coating development
- Wafer bonding and SOI fabrication
- Electrical, thermal, and mechanical material testing
- University cleanroom and student projects
- Process-monitor and equipment-calibration samples
Information Needed for a Silicon Ingot Quote
Include as many of the following specifications as possible when requesting silicon ingot material:
- CZ, FZ, magnetic CZ, or NTD material
- Ingot diameter and required length
- Crystal orientation, such as <100>, <110>, or <111>
- n-type, p-type, intrinsic, or undoped material
- Dopant, such as phosphorus, boron, arsenic, or antimony
- Target resistivity range
- Minority-carrier lifetime requirements
- Oxygen and carbon limits
- Flat, notch, or edge-orientation requirements
- Surface condition and dimensional tolerances
- Certification or characterization requirements
- Quantity and application