Silicon Carbide (SiC) 4H and 6H Wafers in Stock

university wafer substrates

Silicon Carbide Wafers for Electronic Devices Operating at High-Temperatures High-Voltage

Get Your Quote Fast

What are Silicon Carbide Wafers Used For?

Silicon carbide (SiC) Wafers Strength and ability to handle high-power and high-frequency makes a superior, but difficult material to work with compared to Silicon and Gallium Arsenide Wafer.

Silicon Carbide based devices are used in:

Short wavelength opto-electronic
High temperature
Radiation resistant applications


Silicon Carbide Wafers For Electronic Devices

Below are just some of the SiC Wafer Inventory that we have in stock. Please let us know if you can use or if you would like us to quote you on something else?

FZ Si Dia Type/Dopant Ori Res ohm-cm Pol Thick(um) Comments
25.4mm Undoped [100] >2,000 SSP 280 Intrinsic Float Zone
50.8mm N/Ph [111] >200 SSP 200 2 FLats back-side Alkaline etched
76.2mm Undoped [100] >5,000 SSP 500 Undoped Float Zone
100mm P/B [111] 40-60 SSP 255 Buy as few as one
150mm Undoped [100] >10,000 DSP 650um Hard to Find
200mm Undoped [100] >1,000 SSP 725um FZ SI TTV <6um, Bow <10um,Warp<25um

#products #vehicles #applications #lighting

Cree is an innovator of Wolfspeed(r ) power and radio frequency ( RF ) semiconductors, lighting class LEDs and lighting products. [2]

Cree's LED product families include blue and green LED chips, high - brightness LEDs and lighting - class power LEDs targeted for indoor and outdoor lighting, video displays, transportation and specialty lighting applications. [2]

Cree's Wolfspeed product families include silicon carbide materials, power - switching devices and RF devices targeted for applications such as electric vehicles, fast charging, inverters, power supplies, telecom and military and aerospace. [2]

Epitaxial growth systems for power devices are expected to find more widespread use in electric vehicles ( EVs ) and other applications. [3]

In the coming years, SiC products will expand into application fields such as robotics, industrial power supplies, traction and variable speed drives. [6]


Infineon Technologies and Cree have inked an agreement on the strategic long - term supply of silicon carbide ( SiC ) wafers. [6]

The market for SiC materials is booming, recently reflected by STMicroelectronics, a multinational electronics and semiconductor manufacturer, purchasing $ 120 million of advanced 150 mm silicon carbide wafers to address the demand ramp - up for silicon carbide power devices. [14]

The agreement governs the supply of a quarter billion dollars of Cree's advanced 150 mm silicon carbide bare and epitaxial wafers to STMicroelectronics during this period of extraordinary growth and demand for silicon carbide power devices. [2]

ST Micro just announced an agreement to acquire 55 % of Swedish silicon carbide wafer manufacturer Norstel AB with an option to acquire the remaining 45 % for a total purchase price of $ 137MM. [13]

#Grade #offer #Prime

All 100-mm Prime Grade SiC wafers from Dow Corning offer consistently excellent mechanical characteristics to ensure compatibility with existing and developing device fabrication processes. [7]

Each successive Prime Grade wafer tier under Dow Corning's new product grading structure offers tighter tolerances for defect density and other critical performance properties that allow customers to precisely balance wafer quality and price, depending on the demands of their specific device applications. [7]

We have worked closely with the materials engineers to ensure our new equipment will offer a premium wafer and competitive cost of ownership. [3]

Efforts to develop 150 mm 4H SiC bare wafer and epitaxial substrates for power electronic device applications have resulted in quality improvements, such that key metrics match or outperform 100 mm substrates. [9]


In power semiconductor industry, Silicon Carbide ( SiC ) based devices become a prominent alternative in compared to Silicon ( Si ) based device due to its superior characteristics. [12]

In compared to the silicon carbide ( SiC ) devices, the other semiconductors are not able to perform under extreme condition [ 1 - 2 ]. [12]

At high junction temperature, the turn - off voltage performance of the Silicon carbide ( SiC ) devices get worse but in compared to silicon ( Si ) devices, it's much better. [12]

The reverse recovery time of silicon carbide ( SiC ) device totally depends on the internal device parameters and the external operating conditions. [12]

In recent year, Silicon carbide ( SiC ) device has capabilities to replace the silicon ( Si ) device due to the feature like high voltage blocking capability, high temperature operation capability, and a much lower on - resistance in compare to silicon device. [12]

#electronics #technology #material

With promising applications in power electronics, hostile - environment electronics, and sensors, there is considerable industrial interest in SiC as a material for electronics. [5]

The eventual success of SiC as an electronic technology will depend on the close interplay of research in fundamental material science with progress in design of electronic devices and packaging. [5]

We review the current status of SiC electronics from a materials perspective - highlighting current difficulties and future opportunities for progress. [5]

For the past decades, silicon- and gallium arsenide - based technologies have paved the way for many electronic innovations in RF wireless and power switching converter systems. [11]

Silicon carbide is the future of power electronics, and CHS offers the potential to overcome the historic limitations of SiC semiconductor manufacturing in a cost effective manner. [14]

#screw #dislocation #diameter #inches #density

The count of total 1c screw dislocations represents a count of total 1c screw dislocations on the surface after an etch that preferentially emphasizes screw dislocation defects. [8]

In another aspect, the invention is a SiC semiconductor precursor wafer having a diameter of at least about 3 inches and a 1c screw dislocation density of less than about 2500 cma2. [8]

Each field - effect transistor includes a bulk single crystal silicon carbide substrate wafer of at least about 3 inches diameter and having a 1c screw dislocation density of less than 2500 cma2. [8]

The wafer is a silicon carbide wafer of the 4H polytype, having a diameter of at least about 3 inches and a 1c screw dislocation density on its surface of less than 2500 cma2. [8]

#transistors #effect #field #metal #invention

These include next - generation switching devices like metal - oxide - semiconductor field - effect transistors ( MOSFETs ), junction gate field - effect transistors ( JFETs ), insulated - gate bipolar transistors ( IGBTs ) and bipolar junction transistors ( BJTs ) or pin diodes. [7]

Additional devices that may be included are junction - field effect transistors, hetero field effect transistors, diodes, and other devices known in the art. [8]

FIG. 6 is a schematic cross - sectional view of a metal semiconductor field effect transistor in accordance with the present invention. [8]

In another aspect, the invention is a plurality of metal oxide semiconductor field effect transistors ( MOSFETs ) 42 formed on low defect 3 inch silicon carbide substrate 44. [8]

#materials #deposition #films #quality

Essentially, it is a method for turning a single high - quality SiC wafer into multiple high - quality SiC wafers. [4]

SiC, specifically its b - SiC poly type, offers outstanding physical and chemical properties, making it a suitable material for low cost and high - quality thin films capable of large - scale deposition in power electronics. [14]

CHS can do what other silicon precursor materials can not, deposit SiC films on semiconductor wafers with low defect densities and high structural quality, all at a lower operational cost. [14]

It undergoes many microfabrication processes, such as doping, ion implantation, etching, thin - film deposition of various materials, and photolithographic patterning. [0]

Furthermore, CHS allows for facile p - doping of materials into the b - SiC films, and due to the methods of deposition amenable to a reagent such as CHS continuous growth without unintentional secondary deposits can be achieved. [14]

#crystals #sublimation #defects

Current seeded sublimation techniques for the production of large bulk single crystals of silicon carbide typically result in a higher than desired concentration of defects on the growing surface of the silicon carbide crystal. [8]

No. 10/628,188 filed Jul. 28, 2003 for Reducing Nitrogen Content in Silicon Carbide Crystals by Sublimation Growth in a Hydrogen - Containing Ambient; Ser. [8]

Accordingly, producing larger high quality bulk single crystals of silicon carbide with low 1c screw dislocation defect levels in crystals formed in the seeded sublimation system, in order to reduce the total number of defects in the produced crystals remains a constant technical and commercial goal. [8]

Although the density of structural defects in silicon carbide bulk crystals has been continually reduced in recent years, relatively high defect concentrations still appear and have been found to be difficult to eliminate, e.g. Nakamura et al ., aUltrahigh quality silicon carbide single crystals, a Nature, Vol. [8]

#voltage #current #problems

Such defects reduce device yields, and inhibit the cost - efficient manufacture of large - area, next - generation power electronic devices with higher current ratings. [7]

In addition, the superior substrate quality in this tier can benefit high - voltage ( 3.3 kV and higher ) and high - current device designs. [7]

This product is for the manufacture of semiconductor power units that are attracting attention in their application withelectric power equipment due to their ability to more efficiently handle high voltages and high currents in comparison with conventional semiconductor devices. [3]

Thus, increasing the quality of large single crystals that can be used to fabricate large surface area devices for high - voltage, high current applications remains a worthwhile goal. [8]

Among all the polytype devices, the 3C - SiC has main drawback that it has low bandgap and low breakdown voltage. [12]

#technology #products #industry #development #manufacturing

Smart Cut technology is currently in use for the manufacture of silicon - on - insulator ( SOI ) products widely adopted by chip manufacturers. [4]

Recent acquisition of state - of - the - art technologies for SiC wafer production from DuPont extends the company's capabilities in developing and manufacturing semiconductor wafers. [3]

As a leading global company of semiconductor and flat panel display ( FPD ) production equipment, Tokyo Electron ( TEL ) engages in development, manufacturing, and sales in a wide range of product fields. [3]

Today, the technology is inherited to wide variety of products that are essential in everyday life, including materials and components used in the information / telecommunication industry and the automotive industry. [3]

SK Siltron has been part of the semiconductor industry in Korea and elsewhere for more than 35 years, pursuing global leadership in semiconductor development through fundamental competitive innovation in technology, manufacturing, infrastructure and talented people. [3]

#layer #type

In soft baked the silicon carbide wafer is heated at 110degC for 1min 30sec, and in the hard baked the silicon carbide wafer is heated at 125degC for 2min 15sec. [12]

For silicon carbide, Nitrogen or Phosphorous are the N - type dope and boron or aluminum are P - type dope which are entrenched on channel layer. [12]

Group III nitride layers on silicon carbide substrates are a basic feature of certain types of light emitting diodes ( LEDs ). [8]

The procedure to obtain a pattern on the positive photoresist S1813 layer over the Silicon Carbide wafer is called photo - lithography. [12]

The fundamental properties of silicon carbide ( SiC ) polytypes and the silicon ( Si ) semiconductor is given in Table 1. [12]

#defects #presence #influence #epilayers

They appear very efficient in solving, to a large extent, the presence of extended defects in 3C - SiC(100 ) oriented epilayers. [10]

The presence of a large number of screw dislocations can also lead to the presence of other defects, such as micropipes and hexagonal voids. [8]

As the defect density is deeply related to the size of the 3C - SiC Schottky diodes, this behavior clearly highlights the influence of the defect towards the electrical characteristics of power devices. [10]

From the abovementioned developments, one can say that a broad knowledge of the different kinds of defects in 3C - SiC epilayers exist but, in comparison, few works have been reported on their influence on the electrical degradation they imply. [10]

Since decades, many efforts have been done to improve the crystalline quality of 3C - SiC grown on Si substrate using CVD, but defects are still present. [10]

#dies #area #mm #cost

Converting to larger 450 mm wafers would reduce price per die only for process operations such as etch where cost is related to wafer count, not wafer area. [0]

Lithographer Chris Mack claimed in 2012 that the overall price per die for 450 mm wafers would be reduced by only 10 - 20 % compared to 300 mm wafers, because over 50 % of total wafer processing costs are lithography - related. [0]

This formula simply states that the number of dies which can fit on the wafer can not exceed the area of the wafer divided by the area of each individual die. [0]

A unit wafer fabrication step, such as an etch step, can produce more chips proportional to the increase in wafer area, while the cost of the unit fabrication step goes up more slowly than the wafer area. [0]

#stress #growth #direction #oriented

In 3C - SiC(100 ) oriented epilayers, twins are visible as inclined domains respectively to the ( 100 ) growth direction. [10]

Twins are also present in 3C - SiC(111 ) oriented layers where they can also be observed parallel to the growth direction ( basal double positioning domains ) [ 55 ]. [10]

In case of 3C - SiC(100 ) growth, the residual stress can be either compressive or tensile whereas it has always been observed tensile in case of 3C - SiC(111 ) epilayers. [10]

The nucleation of 3C - SiC on two different Si terraces leads to the formation of two SiC grains growing along the ( 100 ) direction but presenting an opposite atomic stacking arrangement along a < 111 > direction [ 47 ]. [10]

#mm #measured #sample #region

Total dislocation densities and threading screw dislocation densities measured for 150 mm wafers were ~4100 cm-2 and ~100 cm-2, respectively, compared with values of ~5900 cm-2 and ~300 cm-2 measured for 100 mm wafers. [9]

The average lattice bow for the substrate only wafer, sample A, is calculated to be ~ 10 um across the entire measured region. [1]

Table 1 Results of the measured doping, surface bow, calculated standard deviation ( s ) in lattice strain and LPC, and FWHM for the three 150 mm SiC wafers. [1]

Epilayers grown on 150 mm substrates likewise exhibit quality metrics that are comparable to 100 mm samples, with median thickness and doping sigma / mean values of 1.1 % and 4.4 %, respectively. [9]

A 1 x 1 cm region from sample A is magnified to show the dot - like contrast, which was counted to be ~ 104 cm-2, typical of good quality SiC substrate wafer. [1]

#seed #source #temperature #crystal #holder

Annealing the seed holder 28 prior to sublimation growth prevents the seed holder 28 from undergoing significant distortion during crystal growth at SiC sublimation temperatures. [8]

A seed holder 28 typically holds the seed 22 in place with the seed holder 28 being attached to the susceptor 14 in an appropriate fashion. [8]

Annealing the seed holder 28 also minimizes or eliminates temperature differences across the seed 22 that would otherwise tend to initiate and propagate defects in a growing crystal. [8]

In a typical silicon carbide growth technique, the seed crystal and a source powder are both placed in a reaction crucible which is heated to the sublimation temperature of the source and in a manner that produces a thermal gradient between the source and the marginally cooler seed crystal. [8]

#energy #band #eV #gap

The band gap energy of silicon carbide change from 2.3 eV for 3C - SiC to 3.2 eV for 4H - SiC. [12]

In L - valley the conduction band minima and valence band maxima at k [? ] 0 where the energy band gap of 4H - SiC is 3.24eV respectively. [12]

The bandgap energy in t valley differs from 5 - 6 eV and the bandgap energy gap in L valley is ( EL ) is 4 eV. [12]

In Figure 2.10 it displays the graph of temperature versus the excitonic energy gap of SiC, and in Figure 2.11 displays the energy band diagram for 3C, 4H and 6H SiC materials at different temperatures. [12]

NOVASiC also provides 4H - SiC on 4H - SiC and 3C - SiC epitaxy on silicon - useful templates for nitride growth. [3]

#ion #Cross #atoms #grid #procedure

The fundamental variable to utilize ion implant procedure is to govern ions and have constancy of the ion over the silicon carbide wafer. [12]

Fig 3.2 shows 6H - Silicon - Carbide MESFET cross sectional perspective and Fig 3.3 shows Cross - sectional perspective of an ion implant machine. [12]

In the host grid atoms, the atoms are blocked on account of the electronic and atomic ceasing system which is in charge of inelastic impact and flexible crash [ 77 ]. [12]

The procedure is done to settle the dilapidation crumbling of the ion implant in the cross section or to conform the film quality developed on the crystal grid. [12]

A Cross - sectional perspective of the silicon carbide MESFETs is appeared underneath with its doping focuses after the ion implant procedure. [12]

#polishing #lapping #grinding #solution #process

Revasum has developed a streamlined grind and polish process that eliminates conventional lapping and diamond polishing steps and the associated issues. [3]

DISCO is a total solution provider for Dicing ( Kiru ), Grinding ( Kezuru ) and Polishing ( Migaku ) technologies. [3]

PR Hoffman Machine Products Inc. is a manufacturer of double sided and single sided Lapping and polishing machines, lapping and polishing carriers and single side polishing templates. [3]

PR Hoffman offers experienced sales and engineering staff to help you customize the best solution for all of your lapping and polishing processing needs. [3]

Revasum understands the challenges of working with SiC and has applied our knowledge of SiC grinding, prime silicon substrate polishing and CMP, to develop a unique solution that truly makes polishing SiC easy. [3]

#layer #BPD #glide #region #doping

Average BPD glide in the low doped sample was calculated to be ~ 65 um for the 10 um thick epitaxial layer. [1]

The BPD glide process leaves behind short BPD segments that appear as dots leading up to the BPD line as observed. [1]

Hence by mapping the Dd / d component, the influence of doping can be correlated to the BPD glide during epitaxial layer growth. [1]

If we assume a linear dependence of BPD glide with epitaxial layer thickness, for 30 - 60 um thick epitaxial layers ( for 3.3/6.5 kV devices ), we could expect BPD glide occurring during epitaxial growth higher than 0.2 - 0.4 mm. [1]

The sample presented successive 1-um - thick layers with a nitrogen doping level ranging from 1017 cm-3 to 5 x 1018 cm-3, separated by nonintentionally doped layers. [10]

#art #description #claims #combinations #invention

Nevertheless, the specification and claims should be read with the understanding that such combinations are entirely within the scope of the invention and the claims. [8]

Such further enclosures are, however, less relevant to the invention and are omitted herein to help clarify the drawing and description. [8]

The structure and operation of MOSFETs, and of combinations and variations of MOSFETs, is well understood in this art and thus FIG. [8]

Accordingly, for the sake of clarity, this description will refrain from repeating every possible combination of the individual steps in an unnecessary fashion. [8]

The structure and operation of these ( and other ) devices are well - understood in this art and can be practiced using the substrates described and claimed herein without undue experimentation. [8]

#maps #variation #peaks #Fig #urad

The X - ray peaks that were collected are generally single peaks with very small peak widths ( ~ 15 urad ), and the repeatability of the goniometer is 1 urad. [1]

In the case of the LPC maps, shown in the bottom row of Fig. 2, the range of the color map is + - 1,000 urad, which is ~ 10 times larger than the Dd / d variation observed in their respective maps. [1]

Hence, for maps of sample A the diffraction peaks are from the substrate and for samples B and C the diffraction peaks are primarily from the epitaxial layers. [1]

In the top row of Fig. 2, the variation of lattice spacing, Dd / d, is shown for the three SiC wafers. [1]