What is the layer structure of an SOI wafer?

An SOI wafer consists of three layers: 1) The Device Layer (top silicon where circuits are built), 2) The Buried Oxide or BOX (insulating SiO2 layer), and 3) The Handle Wafer (thick silicon substrate for mechanical support).

What is the difference between Thin and Thick SOI?

Thin SOI typically has a device layer <1µm (often <220nm for photonics) and is made via ion implantation (Smart Cut). Thick SOI has device layers from 2µm to 100µm+, made via bonding, and is used for MEMS and power devices.

Do you sell SIMOX or Bonded SOI?

We supply both. SIMOX is often used for thin uniform layers, while Bonded SOI allows for thicker, customizable device and oxide layers.

Silicon-on-Insulator (SOI) Wafers: Thin & Thick Device Layers

Q: Do you sell SIMOX or Bonded SOI?

We supply both. SIMOX is often used for thin uniform layers, while Bonded SOI allows for thicker, customizable device and oxide layers.

📡 RF-SOI In Stock

200mm High-Resistivity Handle
Device: 70nm (Thin)
BOX: 145nm
Handle: >1,000 ohm-cm
Ideal for RF switches and low-loss applications.

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Why UniversityWafer?

Single Wafers: No need to buy a full cassette of 25. Perfect for prototyping.
Custom Bonding: We can create custom thick-SOI stacks for MEMS.
Dicing Services: We can dice wafers into 10x10mm chips for you.

SOI Inventory

Below is just a small list of our very large Silicon-on-Insulator inventory of ourr Bonded and Thin-Device-Layer-SOI.

Type	Diameter	Device	BOX	Handle	Application	Action
Thin SOI	100mm	220nm	3,000nm	525µm	Photonics / Waveguides	Buy
Thin SOI	200mm	55nm	145nm	725µm	FD-SOI / Logic	Buy
Bonded	100mm	2µm	1µm	500µm	MEMS / Sensors	Buy
Bonded	150mm	5µm	2µm	675µm	Power Devices	Buy
Thick	200mm	50µm	2µm	725µm	Microfluidics	Buy

Understanding SOI Layer Structure

Silicon-on-Insulator wafers are engineered substrates composed of three distinct layers. Understanding this structure is key to selecting the right wafer for your application.

1. The Device Layer (Top Silicon)

This is the active silicon where your transistors, sensors, or waveguides are fabricated.

For Photonics: Usually 220nm or 340nm to confine light.
For MEMS: Often 10µm to 100µm to provide mechanical mass for accelerometers.

2. The Buried Oxide (BOX) Layer

This SiO2 layer electrically and optically isolates the device layer from the handle.

Standard: 1µm to 3µm is common for optical isolation.
RF-SOI: May use special "trap-rich" layers under the BOX to further improve linearity.

3. The Handle Wafer

The bottom substrate that provides mechanical strength. For RF applications, we offer High-Resistivity (>1k ohm-cm) handle wafers to reduce signal loss and crosstalk.

Manufacturing Methods: SIMOX vs. Bonded

We supply SOI wafers manufactured using the two primary industry methods:

SIMOX (Separation by Implantation of Oxygen)

Oxygen ions are implanted at high energy into silicon, followed by annealing. This creates a very thin, uniform BOX layer.

Best for: Thin-film devices, radiation-hardened electronics.

Wafer Bonding (Bonded SOI)

Two silicon wafers are oxidized and fused together, then one is ground down to the desired thickness.

Best for: MEMS, Power devices, and applications requiring thick Device or BOX layers.