(112) Oriented Silicon Wafers for R&D

university wafer substrates

What is (112) Orientation Silicon Wafers Used For?

In silicon semiconductor thin films, X-ray diffraction of the absorber layers reveals that the preferred (112) orientation correlates with better device performance. The primary reason for the superior performance of the 112 orientation is the decreased series resistance of the absorber layer. Moreover, admittance spectroscopy shows a higher absorber conductivity at low temperatures.

If you're a semiconductor engineer and would like to know more about this technique, this article will provide you with the answers to your questions.

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(112) Silicon Semiconductor Wafer

The silicon semiconductor substrate of the present invention is planarized at a 110-degree-K axis and has an 112-degree-angle orientation. Then, the main surface of the silicon semiconductor substrate is cleaned with an aqueous solution of ammonium fluoride. The result is that the surface becomes flat and is perpendicular to the arrow mark OA'. The orientation control of the front and back surfaces is eliminated, and there is no risk of selecting the wrong surface.

The present invention provides a method for forming steps on a silicon semiconductor substrate that includes a 110-level plane and a plane inclined from the 110-degree orientation. This approach is useful for the fabrication of high-speed integrated circuits. One of the key advantages of the new technique is the ability to minimize surface roughness and increase device efficiency by lessening the occurrence of defects. The technique is also applicable to silicon wafers.

The OA' process can be used for different types of semiconductor devices. It requires a silicon substrate that has a plane inclined from the 110-plane. In this case, the silicon semiconductor substrate is referred to as "Orientation flat." Its main surface is called the'main surface' of the device. In contrast, the front and back surface are identical. This makes the design possible. This method is also more complex than its mirror polished counterpart.

The AFM image of pure Al single crystals shows terraces and steps with the 110-degree orientation. The width of the terrace is 100-nm. The angle of the steps and terraces is the same at both angles. The kinks and steps are formed by a single atom at a time. The kinks and lattice rotation of the B-oriented crystals correspond to the differences between the B and C-orientation.

Surface planarization is a method of decreasing the roughness of a silicon semiconductor substrate. Using surface planarization, terraces are formed between steps on the silicon semiconductor substrate. They are planar on an atomic level. In addition, carriers flowing in the 110-orientation orientation flow directly under the flat terrace and are not scattered by the steps. This reduces the surface roughness of the silicon semiconductor, resulting in high mobility.

The main surface of a silicon semiconductor is inclined towards the 110-oriented plane. The plane is mirror-polished, and the surface is inclined to the orientation of the silicon substrate. The AFM images are highly accurate, and can help you determine which of the two orientations is correct for your silicon-oriented chip. Once you've determined the AFM planes, you'll have the best possible chance of succeeding with your next project.

The main surface of a silicon semiconductor substrate in the 112-orientation is inclined at an angle of about 8 degrees toward its orientation. This angle is known as the slope of a silicon substrate. Assuming that a silicon substrate is inclined at a steeper angle, it is considered to be in the 112-orientation. A typical insulating-silicon device with this orientation is known as a silicon wafer.

 

(112) Orientation Silicon Wafers

Below are just some of the silicon wafers with have with (112) orientation. Please let us know if you can use, or if you need another spec for us to quote.

Item Qty Type/Dopant Ori Dia (mm) Thck (μm) Surf. Resistivity Ωcm
N445 7 n-type Si:P [112-5.0° towards[11-1]] ±0.5° 6" 875 ±10 E/E FZ >3,000
SEMI, 1Flat (47.5mm), TTV <4μm, Surface Chips
G343 25 n-type Si:P [112-5° towards[11-1]] ±0.5° 6" 1,000 ±10 C/C FZ >3,000
SEMI, 1 JEIDA Flat (47.5mm), Empak cst, TTV<4μm, Lifetime>1,000μs
K343 25 n-type Si:P [112-5° towards[11-1]] ±0.5° 6" 800 ±10 P/P FZ >3,000
SEMI, 1 JEIDA Flat (47.5mm), Empak cst, TTV<4μm, Lifetime>1,000μs
L343 25 n-type Si:P [112-5° towards[11-1]] ±0.5° 6" 950 ±10 P/P FZ >3,000
SEMI, 1 JEIDA Flat (47.5mm), Empak cst, TTV<4μm, Lifetime>1,000μs
5739 10 n-type Si:P [112-5° towards[11-1]] ±0.5° 4" 765 P/P FZ ~100
SEMI Prime, 1Flat, Empak cst, TTV<3μm
S5767 68 n-type Si:P [112-5° towards[11-1]] ±0.5° 4" 762 P/P FZ ~100
SEMI Prime, 1Flat, Empak cst, TTV<3μm
5731 25 n-type Si:P [112-3° towards[11-1]] ±0.5° 4" 762 P/P FZ >100
SEMI Prime, 1Flat, Empak cst
B987 11 n-type Si:P [112-5° towards[11-1]] ±0.5° 4" 795 E/E FZ >100
SEMI, 1Flat, in Empak, TTV<4μm, Lifetime>2,000μs
S5858 6 n-type Si:As [112-3° towards[111]] ±0.5° 3" 890 P/E 0.002-0.003
Prime, 2Flats, Empak cst
5764 3 n-type Si:P [112-3° towards[11-1]] ±0.5° 3" 508 P/P FZ 50-150
1Flat, Empak cst
H151 2 n-type Si:P [112] ±0.5° 4" 500 P/P 11-15
SEMI Prime, 1Flat, in Empak cassettes of 2 wafers