UniversityWafer supplies N-type and P-type doped silicon wafers with controlled resistivity, crystal orientation, diameter, thickness, and surface finish. Compare P-type silicon wafers doped with boron and N-type substrates doped with phosphorus, arsenic, or antimony for semiconductor devices, MEMS fabrication, sensors, power electronics, and materials research.
Doped Silicon Wafers for Nanofluidic Devices
A researcher requested help with the following project.
I’m in the process of searching for silicon wafers to be used in the generation of nanofluidic devices. Our initial thought is to try to use silicon wafers with the exact thickness of the channel depth we wish to create lithographically (5 nm). It seems to be the usual minimum thickness is 10 nm. If this is unfeasible or has a sizeable additional cost, we’re looking at using 10 nm and 100 nm thermal oxide thickness layers and working out the etch time to provide the desired depth. I think 100 mm diameter seems reasonable, but I’m unsure about what dopant we should use. The final step will be anodic bonding of a glass layer to the top of the oxide surface if that makes a difference.
Also, we’re looking at using anodic bonding to seal these chips, and I was wondering if the borofloat 33 glass would work? If so I was looking at an order of 10x of the below silicon wafers and 10x of the matching borofloat glass. Also, If you have any recommendations on anodic bonding temperature, voltage, and applied force it would help us in minimizing troubleshooting.
UniversityWafer, Inc. Answered:
You probably want Silicon wafers with either (100) or (110) crystallographic orientation {not (111)}. (110) wafers let you etch deep trenches with almost vertical walls.
4"Ø wafers are actually 100.0±0.5mm in diameter. Standard thickness is 500 or 525±25µm. Wafers thicker than that or thinner than 380µm cost more.
p-type, Boron doped Silicon wafers are most common, although for your application the dopant is immaterial. Wafer resistivity should be (1-1,000)Ohmcm. Lower resistivity implies more impurities and higher resistivity costs more.
Silicon is crystallized by CZ or FZ process. CZ Silicon invariably contains about 20ppma of Oxygen which can affect activity of some etchants. FZ costs more.
Wafers can be one-side-polished or double-side-polished.
If you are dealing with structures 10nm deep then you want extremely well polished wafers. All Silicon wafers are polished to a surface roughness of about 0.5nm rms (as determined by AFM over an area of about 2×2µm). However, wafer thickness variation across the entire wafer is much larger. SEMI standard calls for Total Thickness Variation (TTV) of 10,000nm. Wafers can be polished to a TTV of 1,000nm but at significant extra cost.
DRY Thermal Oxide is the Silicon Oxide of choice for your application. We can grow 5nm of SiO2 (allowing for native Oxide layer) but with thickness tolerance of ±15%. At Oxide thickness of 50nm we can guarantee tolerance of ±5%. Surface roughness and TTV of Silicon wafers with Thermal Oxide layer are essentially those of the underlying Silicon wafers.
Item Qty. Description GV69. 10/25 Silicon wafers, per SEMI Prime, OxP/POx 4"Ø×500±25µm, FZ n-type Si:P[100]±0.5°, Ro=(50-70)Ohmcm,
both-sides-polished (both with 1,000ű5% oxide),, SEMI Flat (one),
Sealed in Empak or equivalent cassette, MCC Lifetime>1,000µs.
Reference #254311 for specs and pricing.
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What Are Antimony-Doped Silicon Wafers Used For?
Antimony-doped silicon wafers are n-type semiconductor materials where antimony (Sb) atoms are used as donor dopants to introduce free electrons into the silicon lattice. These wafers have specialized applications where high electron concentration, thermal stability, and radiation resistance are important.
✅ Common Applications of Antimony-Doped Silicon Wafers
1. Power Electronics
High-voltage devices like diodes and power MOSFETs
Sb provides deep-level donor states, which are more thermally stable than phosphorus or arsenic at high temperatures.
2. Radiation-Hardened Electronics
Used in aerospace and military systems due to Sb’s superior resistance to radiation-induced degradation.
Applications include satellites, space probes, and nuclear instrumentation.
3. High-Temperature Electronics
Sb-doped wafers are more thermally stable than phosphorus-doped ones, making them suitable for engine control systems, sensors, and devices in harsh environments.
When high conductivity stability is required over temperature variations, Sb-doped wafers may be selected.
🔧 Specifications Typically Associated with Sb-Doped Wafers
Resistivity: Often in the range of 0.001 to 10 ohm-cm
Orientation: <100> or <111>
Type: N-type
Thickness: Customizable (common for MEMS and power devices)
Polish: SSP or DSP depending on application
What Is Doped Silicon?
Doped silicon is crystalline silicon whose electrical properties are intentionally adjusted by adding a controlled concentration of impurity atoms. These dopants determine whether electrons or holes are the majority charge carriers and help establish the wafer’s electrical resistivity. Doped substrates are essential starting materials for transistors, diodes, integrated circuits, sensors, solar cells, MEMS, and other semiconductor devices.
Phosphorus-, arsenic-, and antimony-doped silicon wafers are N-type materials. These Group V donor atoms have five valence electrons. Four participate in bonds with neighboring silicon atoms, while the additional electron can contribute to electrical conduction. Electrons are therefore the majority carriers in N-type silicon.
P-Type Silicon Doping
Boron-doped silicon wafers are the most common P-type substrates. Boron is a Group III acceptor with three valence electrons. When it substitutes for silicon in the crystal lattice, it creates a mobile hole that acts as a positive charge carrier. Learn more about P-type silicon wafers and their research applications.
How Dopant Concentration Affects Resistivity
Dopant species and concentration influence carrier concentration and wafer resistivity. In general, increasing electrically active dopant concentration lowers resistivity, but the required range depends on the device and process. Researchers should specify conductivity type and resistivity separately instead of assuming that every wafer with the same dopant has identical electrical behavior.
Heavily doped silicon wafers are often selected for low-resistance contacts, electrodes, electrochemical devices, and conductive MEMS structures. Higher-resistivity silicon may be preferred when substrate conduction or electrical loss must be reduced.
Total thickness variation, bow, warp, and surface requirements
Optional oxide, nitride, epitaxial, or deposited layers
Doped Silicon for P-N Junctions
Placing P-type and N-type regions next to one another forms a silicon P-N junction. The resulting depletion region and built-in electric field are fundamental to diodes, transistors, photovoltaic cells, LEDs, and many sensors. Device performance depends on the dopant profile, junction depth, carrier lifetime, resistivity, and thermal history.
Doped Silicon Video Overview
Doped Silicon Explained – video loads only after you select play.
