N-type Silicon Wafers for Research & Production

university wafer substrates

N-Type Silicon Substrates

N-type wafers that can be easily redeployed to any number of different types of wafer types for a variety of applications, such as a single-byte, multiple-byte or even a small-bit wafer.

The latter is most commonly used in advanced CMOS devices that implant p-wells, such as microprocessors, microcontrollers and microfluidic devices. N wafers are strongly doped at 1 ohm / cm2 and are suitable for a wide range of applications, from small-bit and single-byte to multi-byte and multiple-bit.

Visit our online store to purchase n-type silicon substrates.

Si Item #2270
50.8mm N-type Arsenic Doped (100) 0.001-0.005 ohm-cm 280um SSP Prime

Si Item #695
76.2mm N-type Phosphorous Doped (100) 1-10 ohm-cm 380um SSP Prime

Si Item #2462
100mm N-type Phosphorus Doped (100) 10-20 ohm-cm 280um DSP Prime

Si Item #2509 - 150mm N-type Antimony Doped (Sb) (111) 0.008-0.02 ohm-cm 675um SSP

Si Item #2518 - 200mm N-type Phosphorus Doped (100) 24-36 ohm-cm 725um SSP

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N-Type Silicon Wafers to Fabricate Low Cost Photodetectors

The following n-type silicon wafers were used to fabricate low-cost UV-Visible broadband photodetectors. Research has discovered many new and wide ranging applications.

Si Item #589 - 100mm N/Ph (100) 1-10 ohm-cm DSP 500um Prime Grade

Here, we use an n-type phosphorous doped silicon wafer with 1–10 ohm.cm resistivity purchased from UniversityWafers. The unit Ohm-cm indicates the bulk resistivity of the silicon wafer. For the etching solution, 0.02 M silver nitrate (AgNO3) and 5 M hydrogen fluoride (HF) aqueous solutions are mixed in 1:1 ratio to prepare the etchant. Silicon pieces are cleaved into 4 cm2 pieces using a carbide-tip pen. Then the silicon pieces are cleaned by ultra-sonication in acetone and isopropyl alcohol for 10 minutes each. 

Research article.

 

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Below are just some of our silicon properties that we have on sale!

  • 1" Undoped Silicon (100) >1,000 ohm-cm 250um DSP
  • 2" P/Boron (100) 1-10 ohm-cm 280um SSP
  • 3" N/Phosphorus (100) 0.01-0.02 ohm-cm 380um DSP
  • 4" Intrinsic Silicon (100) >20,000 ohm-cm 500um DSP
  • 6" P/B (111) <1 ohm-cm 300um SSP
  • 8" Intrinsic (100) >5,000 ohm-cm 750um SSP
  • 12" P/B (100) 10-20 ohm-cm DSP 850um

We have plenty of silicon wafers at a low price and small quantitiesof partial cassettes so you can buy less than 25 wafers and as few as one Si wafer.

We carry a large selection of Silicon wafers with:

Retinal Cells Cultured on Silicon Nanowire by Using UniversityWafer N-type phosphorus substrate

Researchers from Sweden have used our products as their silicon substrate controls. To help their work, flat silicon, phosphorus doped wafers with a resistivity of 1-10 Ohm-cm were used. This was a control substrate. The overall goal of the research was to find a way to deliver drugs to retinal cells for growth.

Silicon Substrate Controls

Control substrates, denominated flat silicon (“flat Si” or “Si flat” in Figures) consisted of (100) n-type (phosphorus) silicon wafers with a resistivity of 1–10 Ohm cm (University Wafer).

Silicon Nanowire Substrate

Si NW substrates were prepared by metal assisted chemical etching (MACE) of crystalline silicon in hydrofluoric acid (HF)/silver nitrate (AgNO3) aqueous solution, as previously described.16 In brief, silicon wafers [as those used as controls: (100) n-type (phosphorus), resistivity of 1–10 Ohm cm], were cleaned in acetone and isopropanol, rinsed in Milli-Q water and immersed in a piranha solution (3[thin space (1/6-em)]:[thin space (1/6-em)]1 concentrated H2SO4[thin space (1/6-em)]:[thin space (1/6-em)]30% H2O2) for 15 min at 80 °C, followed by copious rinsing in Milli-Q water. Arrays of Si NW were obtained by chemical etching of the substrate in HF/AgNO3 (6.3 M/0.02 M) Milli-Q water solution at 55 °C for 10 min. Silver was removed by immersing the substrates in two successive 4 hour-long baths of nitric acid (HNO3) at room temperature, rinsing in Milli-Q running flow during 1 min and further rinsing in a Milli-Q water bath overnight. Fig. 1 shows scanning electron microscopy (SEM) images of the main type of Si NW substrates used in this study, with 4.4 μm long nanowires of diameter ranging from 20 to 120 nm. Nanowires of different lengths (200 nm, 800 nm and 1.8 μm) were also prepared with 1 min, 3 min and 6 min etching durations, respectively. Mechanical properties of silicon.

Publication

See below for a short list of our n type silicon wafers

N-type Silicon

Buy as few as one silicon n-type wafer!

Special!

FZ 6"Ø×25mm n-type Si:P[100],(7,025-7,865)Ohmcm, 1 SEMI Flat We have a large selection of Prime, Test and Mechanical Grade Undoped, Low doped and Highly doped Silicon wafers 1" - 12" Silicon Wafers low doped and highly doped in stock and ready to ship. Examples full and partial silicon wafer cassettes include:

We can custom make wafers in small quantities. We can dice them, thin them to 2um. We have undoped, low doped and highly doped Silicon substrates that are always in stock. 

Typical Client Question regarding silicon wafers:

After looking at your online store, I think we might go with your cheapest silicon wafers, product ID 444. I am in a group that is working on a Senior Design Project to create a biobattery. We need a substrate to pattern with photolithography and subsequently deposit various precious metals on that will catalyze certain reactions and conduct electricity. If you have any advice on specific types of wafers we will need for such nano electronic devices I would be happy to know. Thanks. 

We make nanomaterials in our lab and one approach is using electrical explosion of wires (EEW). We used one of Scott's old Si wafers (doped with B) and broke off a strip of Si that we attached to electrodes in our EEW apparatus. It worked nicely and we are looking to do the same thing with Ge (Germanium Wafer). We need a wafer that is less than 500 microns thick. Fill out the form and receive an immediate quote. See bottom of page for recent Silicon Wafers specials.


Recent Silicon Wafer FAQs

What is surface flatness of silicon wafer?

We have Ultra-Flat Silicon with the following spec

Prime Silicon Wafers 100mm P-type /Boron doped <1-0-0> 490-510 micron 0.005-.020 ohm-cm Semi Std Double Side Polished Total Thickness Variation (TTV)<1 um. These are great for making SOI or MEMS!

What is the roughness value (rms) silicon wafer?


The majority of our Prime Grade wafers have a roughness value Ra<5Å.

What is the definition of silicon wafers?

A Si wafer, or substrate, or silicon is grown in a tube from a seed into a long ingot that is then sliced into various thicknesses used in electronics for the fabrication of integrated circuits and in photovoltaics. The wafer serves as the substrate for microelectronic devices built in and over the wafer and undergoes many microfabrication process steps such as doping or ion implantation, etching, deposition of various materials, and photolithographic patterning. Finally the individual microcircuits are separated (dicing) and packaged.

Do you sell platinised silicon wafers?

Yes! We sell Platinised and thin films of almost all the metals! Just let us know the specs and quantity for an immediate quote!

Do you sell one silicon wafer? If so, how?

Yes! We sell as few as one Silicon wafer. We sell in individual wafer carrier.

How do you clean Si 100 wafer before silicon dioxide is formed for bump production?

The RCA clean is a standard set of wafer cleaning steps which need to be performed before high-temperature processing steps (oxidation, diffusion, CVD) of silicon wafers in semiconductor manufacturing. 

Werner Kern developed the basic procedure in 1965 while working for RCA, the Radio Corporation of America.[1][2][3] It involves the following chemical processes performed in sequence: Removal of the organic contaminants (organic clean + particle clean) Removal of thin oxide layer (oxide strip, optional) Removal of ionic contamination (ionic clean)

Can you resize silicon wafers from 200mm to 100mm?

Yes! We can laser down the wafer so you could get two 100mm from one 200mm wafers including flats!

What is silicon wafer reclaim?

It's when you have a wafer that has thin films or oxide etc on them and we strip and clean them so the wafers can be reused. Often companies that want to save money or protect their intellectual property will reclaim their wafers.

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  • Super Thin Silicon used for Solar Application with >45% effiencies
  • Thick Silicon wafers used as substrates for depositing various films on them, like polymer membranes.
  • Intrinsic Silicon wafers that let circuits built on it act very fast. This is also why one uses SOI wafers.
  • Low resisivity Silicon wafers used by laboratories that use Epi growth reactors.
  • Standard substrates used for npn transistor circuits npn si transistorand optical applications.
  • Inexpensive Silicon wafers used to make ultra-pure and ultra-clean carrier that do not react  with the organic  sample to be analyzed.

N-type Silicon for MOCVD Deposition

Researcher:

I am looking to get quotes for N-type polysilicon wafers for use in MOCVD depositions. I am interested in 3" and 4" wafers with thicknesses between 200-500 um, DSP with doping greater than or equal to 10e17. The crystal quality needs to be suitable for use in a solar cell. I need 25-50 wafers.

UniversityWafer, Inc. Quoted:

N-type polysilicon wafers 4" wafers with thicknesses between 200-500 um, DSP resistivity < 0.1 ohm-cm

Price $Reference #259882

What Single Crystal Silicon Properties Can Be Used to Record Atomic Force Microscopy Image?

Researchers have used the following silicon wafers as an ultrasmooth surface for nanomaterials/nanosheets to take and record Atomic Force Microscopy (AFM) Images.

Item #809
100mm N/Ph (100) 1-10 ohm-cm SSP 500um Prime Grade

What Types of Silicon Wafers Are There?

types of silicon wafersThere are several different types of silicon wafers. SOI (silicon on insulator) wafers are made of a thin, insulator-silicium layer on a silicon substrate. This type of wafer is widely used in the fabrication of MEMS devices and thin Si optical channels. SoI wafers are grown as single crystals with a regular repeating structure, and are sliced from an ingot. The orientation of a silicon wavefront determines its electrical response, and it can be affected by ion implantation, etching, or integration with other materials.

SOI wafers are made with a thin silicon layer on a sapphire substrate. The sapphire insulator is typically un-doped. SOS wafers are used in applications that require electrical insulation. Inseto uses several parameters to distinguish between these two types of silicon wafers. Ultimately, SOS wafers can be divided into three main categories, each with their own advantages and disadvantages.

While un-doped silicon wafers are considered pure, doped silicon wafers contain impurities in the form of dopants. These wafers are generally referred to as intrinsic, extrinsic, or degenerate, depending on how much dopant is present. These are the most commonly used types in industry. A common example of a semiconductor is an LED.

Prime silicon wafers are also known as Device Grade and Particle Grade wafers. They have tighter specs and are most often used for photolithography, particle monitors, and semiconductor devices. Test and reclaimed silicon wafers have a much wider range of specifications and are called N-type wafers. They are also known as P-Type, but have a wider tolerance than prime ones.

Reclaimed wafers are also a form of silicon. These wafers have been used in semiconductor production for many years and are used as the primary component of most semiconductors. These reclaimed wafers are made in the same process as virgin wafers, but have been treated to make them suitable for reuse. These reclaimed wafers are a great way to save money.

Polished silicon wafers are mirror-smooth. Compared to unpolished silicon, they are much more uniform and have a high quality reputation. They meet the age requirements for ULSI. Glass wafers are used where transparency is required. The difference between these two types of silicon wafers is quite large. You should make sure you choose the right material for your particular project.

In semiconductor manufacturing, reclaimed silicon wafers have been stripped of the processing and are called N+. They are the most expensive to manufacture and are used in advanced CMOS devices. They can be obtained from reclaimed silicon wafers as well. These products are considered the most desirable types of silicon wafers. Once they are reclaimed, they are often sold again. But the only difference between these two types is the size.

Reclaimed silicon wafers are different from N-type. They are stripped of all previous processing and are more expensive than N-type. They are usually not transparent. However, transparent silicon wafers are used in optical devices. They are also the most expensive to produce. But they are cheaper than n-type products. This is a huge advantage of reclaimed silicon, as reclaimed silicon is much more durable than n-type.

Prime and N-grade silicon wafers are the same. They are both made from the same basic material. There are some differences, but the same fundamental principles apply to all types. Premium silicon wafers are free of defects that are common with other kinds of silicon. Despite these differences, reclaimed silicon is the most expensive type. If it's a premium grade, it has fewer imperfections.

The undoped silicon wafer is a pure silicon crystal. It's the best type of semiconductor, and is the only one that can be used for sensitive electronics. While it's not the most expensive, it's the least expensive. The only downside is that it's brittle. The silicon wafers are very sensitive to heat. They are easily cracked or chipped. In addition, they can lose their properties if they are heated.

Self-Assembly of Block Copolymers for Nanopatterning

Scientists have use the following wafers for their nanotechnology research.

Silicon (100) wafers (prime grade, 100 mm diameter, n-type, phosphorous doped, resistivity = 5{10 ohm-cm) were purchased from University Wafer. 38% HCl (aq) and 30% NH4OH (aq) were obtained from J. T. Baker; methanol and 30% H2O2 were obtained from Fisher Scienti c; tetrahydrofuran (THF) and toluene were obtained from Caledon Laboratories Ltd. Ultrapure water with > 18 M cm from a Millipore Milli-Q system was used for all experiments. Six sizes of cylinder-forming PS-b-P2VP BCPs were obtained from Polymer Source: PS(125k)-b-P2VP(58.5k), PS(56k)-b-P2VP(21k), PS(50k)-b- P2VP(16.5k), PS(44k)-b-P2VP(18.5k), PS(32k)-b-P2VP(12.5k), and PS(23.6k)- b-P2VP(10.4k). Polystyrene with Mw = 192 kg/mol was obtained from Sigma Aldrich. The metallization salts Na2PtCl4 xH2O and Na2PdCl4 3H2O were obtained from Strem Chemicals.

Please contact us for complete wafer specs.

Which N-Doped Silicon Wafer Has the Highest Electric Conductivity?

There is a great debate about which n-doped silicon wafer has the highest electric conductivity. Among the various options, there are epi-doped silicon and graphene quantum dots. Let's take a closer look at each of these options and see if they really make the most sense for your application.

the silicon conductivity of n-type wafers

Graphene quantum dot

Graphene quantum dots have the highest electrical conductivity of all known materials. The 5.3-nm-thick layers of graphene are soluble in a variety of organic solvents, including tetrahydrofuran and dichloroethane. Furthermore, the material is magnetic.

Graphene quantum dots have unique electronic and optical properties. They are extremely small and exhibit strong quantum confinement and edge effects. Several approaches have been developed to produce these particles. Some include hydrothermal GO reduction, chemical synthesis, and electrochemical approaches.

Graphene quantum dots can be synthesized in two different ways. One method involves water dispersible graphene, and the other uses graphene-based polypyrrole nanocomposites. In both methods, the polymer quantum dots are characterized using UV-Visible absorption spectra, transmission electron microscopy, and electrochemical impedance spectroscopy. The polymer quantum dots composites were then used to create solid-state supercapacitors using PVA/KOH gel as electrolyte. The capacitors performed well, and the researchers were able to observe the correlation between their capacitance and the electrode structure.

In the photodetector, graphene/PbS QD heterostructure photodetectors exhibit the highest D* and R* values in the infrared range. These photodetectors have high R and D* values, and a high response time. In addition, they exhibit high R and D* indices, which are critical performance indices for photodetectors.

Graphene has a plethora of potential applications. The material is the thinnest two-dimensional material in the world, and can be used in high-performance electronics, semiconductors, and electric batteries. Scientists expect to use graphene for devices and electronics in the near future.

Graphene quantum dots have the highest electric conductivity of any known material. Its crystalline structure allows for efficient electron transport. As a result, graphene quantum dots are highly promising candidates for various applications in electrical and thermal technology. These new materials are also able to improve thermoelectric properties of thin films.

Electrical conductivity of graphene quantum dots depends on their chemical and electronic interactions. When graphene quantum dots interact with polymers, their electrical conductivity increases. This effect is further enhanced when the GQDs are bound to PEDOT-PSS. This is because their chains are much larger than GQDs, which increase their electrical conductivity.

Graphene quantum dots can be prepared by a variety of methods. Graphene quantum dots can be synthesized using an electrochemical method. They can be manufactured from various starting materials and have high aqueous solubility. However, the preparation process is complex, and product yields are low.

Epi wafer

GaN is the de facto material for third-generation semiconductors. However, creating a GaN epi wafer of desired thermal resistance and quality is a challenge. The mismatch between the material's lattice constant and thermal expansion coefficient can cause cracks and dislocations within the epi layer.

This process requires large-diameter wafers that are free from vacancies and other defects. The resistance of these wafers is typically in the tens of ohms. This makes the technology suited for high-frequency applications, such as radio-frequency transceiver devices.

Epi wafers are also known as test wafers. These wafers are used for process monitoring purposes, and have less strict surface and bulk property specifications than prime wafers. They are commonly derived from prime wafers that have failed or were rejected during a test phase. Because they do not have backside or flatness specs, they generally perform well.

Higher substrate resistivity levels are also necessary for passive components and wireless chip designs. Today, resistivity levels of more than 40 ohm-cm are required, and they may eventually reach up to 1000 ohm-cm. However, CZ crystals can be grown up to 100 ohm-cm using existing growth methods. The process is similar to that of standard epi wafers, but it can grow to higher resistivity levels without changing the final wafer product.

SOI is another type of semiconductor material. Its three layers consist of a top silicon layer and a buried insulator. The surface silicon layer has a thin layer of silicon on top of a sapphire substrate. The sapphire substrate has a slight lattice mismatch and is used as an insulator. Afterwards, oxygen ions are implanted into the substrate to form a buried oxide layer. This process is called SIMOX and is common in the manufacturing of SOI wafers.

Another process known as direct-bonding allows for a higher-density epielectric material. This method enables the incorporation of mismatched materials and avoids constraints caused by lattice parameter mismatch. It also helps overcome problems associated with high density of threading dislocations.

Electrons in the valence band can be promoted to the acceptor level by an electric field. These electrons then jump into the hole in the valence band, resulting in the flow of electrical current. In p-type extrinsic semiconductors, this is the main charge carrier for current flow.

Sb-doped silicon

It is generally accepted that Sb-doped silicon has the highest electrical conductivity of all semiconductors. This material has a very narrow band gap of 1.12 eV, and the donor level of Sb doped into it is 0.039 eV below the bottom of the conduction band. This makes it an ideal material for transistors.

This material is characterized by its high local and longitudinal electrical conductivity. Researchers have developed a dual plasma method to synthesize nanocrystals of Sb-Sn alloy. The process starts with metalorganic precursors, which are well mixed and then oxidized to form Sb-Sn alloy nanocrystals. The dual plasma method has the advantage of overcoming the problem of surface segregation of resistive phases.

The electrical characteristics of p and n-type silicon are also affected by the presence of natural oxide. In the case of p-type Si substrates, SOD doping results in ohmic contact, with an increase in electrical conductivity of 150 to 1160 S/m2 and 385 to 1390 S/m2 for n-type silicon. Additionally, SOD doping reduces contact resistance, which is beneficial in electronic devices.

In order to study the effect of Sb doping, the electrical conductivity of the Sb-doped silicon was measured using a four-point probe. This technique shows two distinct regions, with an increase at 0.228 J of laser energy, and a decrease after this. When the input laser energy is less than 0.28 J, the process does not cause diffusion of impurity and structural defects.

When Sb is doped in a good crystal, it introduces new energy states within the band gap, which is closest to the energy band of the dopant. In this way, Sb can create states near the conduction band and electron acceptors create states near the valence band. These energy states are called dopant-site bonding energies, or EB. For example, boron in silicon bulk has 0.045 eV of bonding energy, whereas the band gap of silicon is 1.12 eV.