Custom Silicon Wafer Processing Services
UniversityWafer, Inc. provides complete silicon wafer processing services for universities, research laboratories, semiconductor manufacturers, and prototype development projects. From crystal growth and wafer slicing to polishing, oxidation, deposition, dicing, and packaging, we can help meet your exact specifications.
Available processing options include:
- ✔ Single Side and Double Side Polishing (SSP & DSP)
- ✔ Thermal Oxide Growth
- ✔ Silicon Nitride Deposition
- ✔ TEOS and CVD Coatings
- ✔ Wafer Dicing and Scribing
- ✔ Custom Thickness Grinding
- ✔ Prime, Test, and Mechanical Grade Wafers
- ✔ Custom Doping and Resistivity Specifications
- ✔ Research and Prototype Quantities
Whether you need a single prototype wafer or high-volume production processing, our team can provide custom solutions for MEMS, photonics, microelectronics, power devices, sensors, solar cells, and semiconductor research.
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How Are Silicon Wafers Processed?
Silicon wafer processing transforms raw single-crystal silicon into flat, clean, polished substrates used for semiconductor fabrication, MEMS, sensors, photonics, solar cells, and university research. Each processing step improves the wafer’s surface quality, thickness control, cleanliness, and electrical performance before it is used to build microelectronic devices.
Silicon Crystal Growth
Most silicon wafers begin as a single-crystal silicon ingot grown by the Czochralski method. During this process, a silicon seed crystal is pulled from molten silicon to form a cylindrical ingot with a controlled crystal orientation such as <100>, <111>, or <110>. Dopants such as boron, phosphorus, arsenic, or antimony may be added to create p-type or n-type silicon with a specific resistivity range.
Wafer Slicing and Shaping
After crystal growth, the silicon ingot is sliced into thin wafers using precision diamond wire saws. The wafers are then edge-rounded, flattened, and inspected to meet diameter, thickness, bow, warp, and total thickness variation requirements. Common wafer diameters include 25mm, 50mm, 75mm, 100mm, 150mm, 200mm, and 300mm.
Lapping, Etching, and Cleaning
Lapping removes saw damage and improves wafer flatness. Chemical etching is then used to remove subsurface damage and prepare the wafer for polishing. Cleaning steps remove particles, metals, organic residue, and other contaminants that can affect semiconductor device performance.
Wafer Polishing
Silicon wafers can be single-side polished, double-side polished, or chemical-mechanical polished depending on the application. Prime-grade and test-grade wafers often require a smooth, low-defect surface for photolithography, thin-film deposition, oxidation, bonding, and device fabrication.
Oxidation, Deposition, and Etching
Additional wafer processing may include thermal oxide growth, silicon nitride deposition, TEOS oxide, metal films, photoresist coating, dry etching, wet etching, and other custom thin-film processes. These steps allow researchers and device manufacturers to create insulating layers, masks, contacts, and patterned structures on the silicon surface.
Silicon Wafers for Research and Device Fabrication
Processed silicon wafers are used in integrated circuits, MEMS devices, microfluidics, sensors, photovoltaics, power electronics, optical coatings, wafer bonding, and university research projects. Choosing the correct wafer processing specification helps improve repeatability, device yield, and experimental performance.
UniversityWafer, Inc. supplies processed silicon wafers in custom diameters, orientations, thicknesses, resistivity ranges, oxide thicknesses, polish types, and dopant types for research and production.