For a research application, I would like to know more about the preparation and surface topography of the "backside" of an SSP silicon wafer. Can you please tell me what is known about the backside? (Or point me to references about it?)
Single Side Polished (SSP) Silicon Wafers
Single Side Polished Silicon Wafers
We have a wide variety of Single Side Polished (SSP) Wafers in stock. We have thicknesses from 100 micron up to 10mm in thickness. We flatness spec as tight as 1 micron total thickness variation (TTV)
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Single Side Polished Silicon Wafer for Gas Barrier & Separation Behavior of Layer-by-Layer Assemblies Research
Scientists have used our SSP prime grade wafers for their gas barrier research.
Single-side-polished (100) silicon wafers (University Wafer, South Boston, MA) were used as deposition substrates for ellipsometry and atomic force microscopy (AFM).
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What are Single Side Polished Silicon Wafers and Their Applications
The process of machining single-sided polished silicon wafers combines mechanical polishing with optical interferometry. The overall thickness of these silicon wafers can be measured using a high-speed laser. In addition, the process is fast and accurate. The thickness can range from 41 to 122 nm. The wavelength used is typically near infrared, and the wavelength is determined by the number of pulses received by the optical probe.
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| Item | Type/Dopant | Orient. | Diam (mm) | Thck (um) | Pol | Resistivity ohm-cm | Comment |
| K148 | Intrinsic Si: | [100] | 1" | 300 | SSP | FZ >20,000 | Prime, NO Flats, Soft cst |
| D355 | Intrinsic Si: | [100] | 1" | 320 | SSP | FZ >20,000 | Prime, NO Flats, Soft cst |
| 5447 | Intrinsic Si: | [100] | 1" | 500 | SSP | FZ >20,000 | SEMI Prime, 1Flat, hard cst |
| 5275 | P-type Si:B | [100] | 1" | 1,000 | SSP | 130 | SEMI Prime, 1Flat, hard cst |
| L678 | P Si:B | [100] | 1" | 3,000 | SSP | 150 | Prime, NO Flats, Individual cst, Group of 13 wafers |
| 5092 | P Si:B | [100] | 1" | 275 | SSP | 0.0150.020 | SEMI Prime, 1Flat, Soft cst |
| S5554 | P Si:B | [111] ±0.25° | 3" | 400 | SSP | FZ >100 | SEMI Prime, 1Flat, Empak cst |
| 4994 | ntype Si:P | [100] ±0.1° | 3" | 380 | SSP | FZ >5,000 | SEMI Prime, 1Flat, Empak cst |
| I978 | ntype Si:P | [111] ±0.5° | 3" | 380 | SSP | FZ 4,0008,000 | SEMI Prime, 1Flat, in hard cassettes of 1 & 2 wafers |
| E383 | ntype Si:P | [111] ±0.5° | 3" | 380 | SSP | FZ 3,0005,000 | SEMI Prime, 1Flat, in Empak, Lifetime>1,000?s, |
| 6773 | Intrinsic Si: | [100] | 3" | 380 | SSP | FZ >20,000 | SEMI Prime, 1Flat, Empak cst |
| 6116 | P Si:B | [100] | 3" | 5,000 | SSP | 130 | Prime, NO Flats, Individual cst |
| 3014 | P Si:B | [100] | 3" | 250 | SSP | 0.150.20 | SEMI TEST (Scratches), 2Flats, in sealed Empak cassettes of 3 wafers |
| S5843 | P Si:B | [1004° towards[110]] ±0.5° | 3" | 230 | SSP | 0.010.02 | SEMI Prime, 2Flats, Empak cst, TTV<5?m |
| 2248 | P Si:B | [100] | 3" | 300 | SSP | 0.010.02 | SEMI Prime, 2Flats, Empak cst |
| S5844 | P Si:B | [1004° towards[110]] ±0.5° | 3" | 381 | SSP | 0.010.02 | SEMI Prime, 2Flats, Empak cst, TTV<5?m, Cassettes of 4 and 20 wafers |
| C260 | P Si:B | [110] ±0.5° | 4" | 500 | SSP | FZ >15,000 {16,45318,686} | Prime, 2Flats, SEMI Flats, PF at<111>, SF at <111> 70.5° CW from PF, Empak cst |
| 6268 | P Si:B | [110] ±0.5° | 4" | 500 | SSP | FZ >10,000 | Prime, 2Flats, TTV<5?m, SEMI Flats, PF at<111>, SF at <111> 70.5° CW from PF, Empak cst |
| 6927 | P Si:B | [100] | 4" | 525 | SSP | 110 | SEMI Prime, 2Flats, Empak cst |
| 6632 | P Si:B | [100] | 4" | 1,000 | SSP | 15 | SEMI Prime, 1Flat, Empak cst, TTV<5?m |
| 4829 | P Si:B | [100] | 4" | 2,100 | SSP | 1100 | SEMI Prime, 1Flat, Individual cst, Groups of 5 wafers |
| 6521 | P Si:B | [100] | 4" | 2,100 | SSP | 1100 | SEMI Prime, 1Flat, Individual cst, Manual Edges, Grouops of 2 + 10 + 10 wafers |
| 6575 | P Si:B | [100] | 4" | 3,000 | SSP | 130 | SEMI Prime, 2Flats, Individual cst |
| 6592 | P Si:B | [100] | 4" | 5,000 | SSP | 1100 | Prime, NO Flats, Individual cst, Group of 3 wafers |
| 6854 | P Si:B | [100] | 4" | 525 | SSP | 0.10.2 | SEMI Prime, 2Flats, Empak cst |
| 3031 | P Si:B | [1006° towards[110]] ±0.5° | 4" | 525 | SSP | 0.0150.020 | SEMI Prime, 2Flats, Empak cst |
| 6349 | P Si:B | [100] | 4" | 525 | SSP | 0.010.02 | SEMI Prime, 2Flats, Empak cst, TTV<5?m |
| H548 | P Si:B | [100] | 4" | 525 | SSP | 0.0150.00 | SEMI Test, 1Flat, Empak cst |
| 6719 | P Si:B | [100] | 4" | 525 | SSP | 0.0010.005 | SEMI Prime, 2Flats, Empak cst, TTV<5?m |
| 6900 | P Si:B | [100] | 4" | 525 | SSP | 0.0010.005 | SEMI Prime, 2Flats, Empak cst |
| I374 | P Si:B | [111] | 4" | 350 | SSP | 23 | Prime, NO Flats, Empak cst |
| TS043 | P Si:B | [1112.5°] ±1° | 4" | 450 | SSP | 28 {3.84.8} | SEMI Prime, 1Flat, {actually (449457)?m thick}, Empak cst |
| D372 | P Si:B | [1113°] | 4" | 400 | SSP | 0.0150.018 | SEMI Prime, 1Flat, Empak cst |
| TS008 | P Si:B | [111] ±1° | 4" | 380 ±10 | SSP | 0.0100.015 {0.01240.0136} | SEMI Prime, 1Flat, Empak cst, TTV<8?m |
| 4279 | P Si:B | [1114°] ±0.5° | 4" | 525 | SSP | 0.010.02 | SEMI Prime, 1Flat, Empak cst |
| F508 | P Si:B | [111] ±0.5° | 4" | 525 | SSP | 0.010.02 | SEMI Prime, 1Flat, Empak cst, TTV<3?m, Bow<10?m, Warp<30?m |
| G508 | P Si:B | [111] ±0.5° | 4" | 525 | SSP | 0.010.02 | SEMI Prime, 1Flat, Empak cst, TTV<3?m, Bow<10?m, Warp<30?m |
| TS033 | P Si:B | [1114°] ±0.5° | 4" | 525 | SSP | 0.010.02 {0.01400.0186} | SEMI Prime, 1Flat, Backside: HardDamage, Empak cst |
| TS077 | P Si:B | [1114°] ±0.5° | 4" | 525 | SSP | 0.010.02 {0.01400.0186} | SEMI Prime, 1Flat, Empak cst (4+5+5+10+15+20 wafers) |
| TS038 | P Si:B | [1113.5°] ±0.5° | 4" | 525 ±15 | SSP | 0.0070.009 {0.00710.0085} | SEMI Prime, 1Flat, Empak cst, TTV<5?m |
| TS069 | P Si:B | [1113.5°] ±0.5° | 4" | 525 ±15 | SSP | 0.0070.009 {0.00710.0085} | SEMI Prime, 1Flat, Empak cst, TTV<5?m |
| TS031 | P Si:B | [1113.5°] ±1° | 4" | 475 | SSP | 0.0050.020 {0.01380.0150} | SEMI Prime, 1Flat, Backside Acid Etch, Empak cst |
| TS007 | P Si:B | [110] ±0.25° | 6" | 625 ±15 | SSP | 1020 {13.613.9} | SEMI Prime, 1 JEIDA Flat 47.5mm @ <111>±0.5°, LaserMark, TTV<2?m, Warp<10?m,Empak cst |
| TS072 | P Si:B | [110] ±0.25° | 6" | 625 ±15 | SSP | 1020 | SEMI Prime, 1 JEIDA Flat (47.5mm) @ <111>±0.5°, Laser Mark, TTV<3?m, Bow<5?m, Warp<10?m, Empak cst |
| 6427 | P Si:B | [110] | 6" | 675 | SSP | 0.010.02 | Prime, PFlat @ [111]±0.25°, SF @ [111]±5° 109.5° CW from PF, Empak cst |
| TS054 | P Si:B | [100] | 6" | 675 | SSP | 1525 {16.121.7} | SEMI Prime, 1Flat (57.5mm), Empak cst, TTV<5?m |
| 6287 | P Si:B | [100] | 6" | 675 | SSP | 510 | SEMI Prime, 1Flat (57.5mm), Empak cst |
| 6751 | P Si:B | [100] | 6" | 1,000 | SSP | 510 | SEMI Prime, 1Flat (57.5mm), Empak cst |
| 6358 | P Si:B | [1006° towards[111]] ±0.5° | 6" | 675 | SSP | 130 | SEMI Prime, 1Flat (57.5mm), Empak cst |
| N698 | P Si:B | [100] | 6" | 675 | SSP | 1100 | SEMI Prime, 1Flat (57.5mm), Empak cst |
| TS055 | P Si:B | [100] | 6" | 675 ±15 | SSP | 0.010.02 {0.01020.0133} | SEMI Prime, 1Flat (57.5mm), Empak cst |
| 6005 | P Si:B | [100] | 6" | 320 | SSP | 0.001-0.030 | JEIDA Prime, Empak cst |
A laser probe is used to measure the interstitial oxygen content of single-side-polished silicon wafers. It is an 
accurate and reliable method to monitor oxygen concentration in silicon wafers. The laser is mounted on an upper plate and rotates at preset speeds. The upper plate then passes through the upper plate, scanning the surface of the silicon wafer. Once the scanning process is complete, the top-side treatment can be applied to the silicon wafers.
Single-side-polished silicon wafers are characterized by the warpage behavior at the temperature of solder reflow, which is the highest temperature used in packaging processes. The surface is analyzed by 3D digital image correlation, and the coefficient of thermal expansion is measured for each surface. The roughness of the single-side-polished silicon wafer has a higher coefficient of thermal expansion than the mirror-polished one.
Integrated circuits are composed of multiple electronic components, such as semiconductor wafers. Because silicon is a semiconductor material, it is a prime candidate for the manufacture of semiconductors. The thin-film process of silicon wafers results in residual stress, which can cause warpage. This residual stress is the result of grinding the silicon wafers too thin. Furthermore, the process is also difficult on the silicon wafers due to the inhomogeneous nature of the material.
The process of single-sided silicon wafers involves the formation of two sides with different thicknesses. The first side of the silicon is flat, while the other is rounded. These processes can be applied to various types of semiconductors, including RF and microwave circuits. It is possible to make a customised semiconductor for any application. The advantages of this process are many. Aside from the dimensional stability, the single-sided polishes of the silicon wafers have no defect.
Aside from the various applications of single-side silicon, it has also been used in microelectronics. This is a type of technology that can be applied to any type of silicon. For example, there are a variety of different technologies and methods for manufacturing single-sided silicon wafers. Aside from being an ideal substrate, silicon wafers can also be used in microelectronic devices.
The double-side polishing method is a more sophisticated method that is used to make silicon wafers. This process involves the use of a mirror-finish both on the front and back sides. It also allows the production of single-sided silicon wafers. Further, a single-sided polish wafer can be made thinner than a regular silicon. Its thinness and low-density makes it an ideal substrate for semiconductor devices.
A single-sided polished silicon wafer can be produced by the DSP method. It is the most common method for polishing single-sided silicon wafers. The DSP method is often used in semiconductor manufacturing because it can control the thickness of a silicon wafer with minimal error. The process has many advantages. Aside from the low cost, it is easy to install and requires no extra tools. The technology has the potential to make the process fast and accurate.
How Difficult is it to Polish Silicon Wafers?
The polishing process is an intricate one. The thickness of the single-sided silicon wafer can be controlled by an elaborate double-side polishing system. The laser probe has different orientations and the thickness is a crucial factor in the process. The depth of the ion implantation is controlled by the ion implantation. By employing the DSP system, the desired depths are achieved.
A single-sided polished silicon wafer has many advantages. Its atomic flatness makes it easier to manufacture devices. Its high-purity polysilicon is suitable for electronic processing. Moreover, it is a low-cost alternative. It meets electrical specifications and is flexible and scalable, allowing for flexible and customizable manufacturing. The LTC system will control the thickness of the wafers in real-time.
What is the Surface Topography of the "Backside" of an SSP Silicon Wafer?
A researcher from a large US university asked the following.
UniversityWafer, Inc. Replied:
Unlike single-sided polished silicon wafers, which have multiple flat surfaces, the backside of a single-sided polished silicon wafer can have particles. Particles on the backside are previously hidden in the backside roughness. Several EG processes can degrade the polished back surface, but only a small number of them has a significant impact. The authors present an initial approach to modeling back-side particle size.
The Silicon Wafers in carriers and the bottom lapping plate are visible on the double sided planetary lapper.
Polycrystalline silicon is an ultra pure form of silicon. In contrast, a single-side polished silicon wafer has a polycrystalline structure. The backside surface of a single-sided polished silicon wafer is polished using an alkaline process, while the front side is etched with a metal-catalyzed chemical etching process. Although the backside of a single-sided polished silicon wafer is not as smooth and uniform as the front side, it is still acceptable for solar cell fabrication.
The backside of a single-sided polished silicon wafer is highly customizable. The wet chemical etching process enables the optimization of back-side metallization processes, by allowing minor adjustments to the process parameters. This process removes damage on the backside of the silicon wafer and increases the wafer and die's strength and uniformity in surface roughness values. These factors help make the single-sided polishing process more efficient.
The etching process is a two-step process. The first step, called stock removal, removes a thin layer of silicon from the backside of the silicon wafer. The second step, the chemical mechanical etch, is used to remove the rest of the material. After the first step, the silicon wafer is then sent to the final cleaning stage, where a series of clean baths is used to remove trace metals and surface particles.