(111) Silicon Wafers for Research, MEMS & Epitaxy

UniversityWafer supplies (111) silicon wafers for semiconductor research, MEMS, epitaxial growth, microscopy, sensors, photonics and advanced materials development. Available options include prime and research-grade silicon wafers, high-resistivity silicon, float-zone (FZ), p-type, n-type and intrinsic substrates in multiple diameters, thicknesses and polish configurations.

The Si(111) crystal orientation is defined by its Miller index and is used when crystallographic orientation affects etching, epitaxy, cleavage, surface structure or device behavior. Researchers commonly compare (111) wafers with (100) silicon wafers and (110) silicon wafers when selecting substrates for a specific process.

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(111) Silicon Wafers for Scanning Tunneling Microscopy (STM)

A Phd student requested the following (111) silicon quote:

We are working on a project to built or produce Rastertunnel Mikroskop (RTM). The mechanical and software part of this project is almost finished, and after everything is completely done, we are going to calibrate this RTM using silizium @ silicon (111).i am the person who r responsible to this calibrating part of this RTM. i just want to ask if i can get cheaper Siliziumscheibe (silicon disc) (111) from your company. The size of the Silizium is not really matter as long as we can get it for a lowest price. i am looking foward to hear from you as soon as posible

Reference #121515 for specs and pricing.

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How to Verify (111) Silicon Wafer Orientation

The most reliable way to verify a silicon wafer's crystal orientation is to use the supplier specification, primary-flat or notch information, or crystallographic measurement methods such as X-ray diffraction (XRD) and Miller indices. For research applications, confirm the stated orientation tolerance, such as (111) ±0.5°, before processing.

(111) Ori Silicon Wafer is a more complicated type of wafer than the 100-oriented one. It can be a bit more expensive than the 100-oriented wafers, but the etching speed is faster.

Most people don't even know that there are different Oris for silicon wafers! And even fewer people know that the (111) Ori has better etching speed and is easier to cut than the (110) oriented silicon.

If you're looking for a high quality silicon wafer with superior etching speed, then you should definitely consider purchasing a (111) oriented silicon wafer from UniversityWafer, Inc.

What Is a (111) Oriented Silicon Wafer?

Silicon wafers are typically classified based on their crystal Ori, which refers to the specific arrangement of the atoms within the crystal lattice of the silicon. One common Ori is (111), which is characterized by a particular arrangement of atoms in the crystal lattice that results in a hexagonal pattern on the surface of the wafer. This Ori is often used in the production of microelectronic devices because it has several advantageous properties, including a lower surface roughness and a higher electron mobility compared to other Oris. In addition, (111) oriented silicon wafers are often used for applications that require high-quality epitaxial growth, such as the production of high-performance transistors.

The (111) orientation is identified by a three-digit Miller index, which is a notation system used to describe the planes and directions within a crystal lattice. The first digit represents the plane, the second digit represents the direction perpendicular to the plane, and the third digit represents the direction perpendicular to both the plane and the direction. In the case of (111) oriented silicon wafers, the three digits represent the (111) plane, which is a set of parallel planes that intersect at 60-degree angles.

The (111) Ori Silicon Wafer is a more complicated type of substrate than the 100-oriented one. It can be a bit more expensive than the 100-oriented wafers, but the etching speed is faster. This is because the silicon atoms are positioned at an angle of 90 degrees to the primary flat. It is also easier to cut than the 110-oriented wafer, but it is more difficult to fabricate complicated structures on a 111 wafers.

(111) Silicon Wafer Applications

For temperature-sensitive components, a 111-Ori silicon wafer is a good choice as its triangular crystal structure can be less prone to high temperatures. This makes (111) silicon devices that work at higher-temps. (111) Ori silicon wafer has a low refractory index, which can improve the reliability of your components. So, if you need a wafer with high refractoriness, a 111-Ori one is a great choice.

111 silicon wafer applications including MEMS, epitaxy, photonics, scanning tunneling microscopy, semiconductor research, and high-resistivity devices

How to Cleave (111) Silicon Wafers

(111) silicon wafers requires a different method to cleave than (100) orienation.

The 111-Ori wafer is a better choice for high-end electronics and works great in cellular phones.

A 111-Ori silicon wafer is a good choice for temperature-sensitive components. A 111-Ori silicon wafer has a softer surface and can be more easily etched.

The 111-Ori silicon wafer has a significant impact on optical, thermal, and electrical properties. During the fabrication process, it is important to have the correct 111 Ori to avoid any mismatches.

The diffraction method is a reliable way of verifying the 111-Ori silicon wafer. It is a proven method for determining crystal Ori. It is an important factor in semiconductor manufacturing. A diffraction pattern is a picture of the crystal's Ori. The X-ray pattern is the best way to make sure a crystalline wafer is correctly oriented. Moreover, the diffraction pattern is highly accurate, allowing for a 0.5 degree accuracy.

Cleaving (111) Silicon Wafers

Video: How to Cleave (111) Silicon Wafers

(100) vs. (111) Silicon Wafers for MOS and CMOS Devices

The main difference between (100) and (111) oriented silicon wafers is the Ori of the crystals. Typically, the (100) oriented silicon is easier to cleve, and the more orientated the silicon, the better. However, there are also other factors to consider, such as manufacturing cost and complexity. Nevertheless, the 100-oriented silicon wafers are more commonly used for MOS devices.

The higher-order (111) surface provides an 80% increase in hole mobility, but the process is much more complicated. The underlying (100) surface is oriented in a way that prevents holes from moving. This is a major drawback, but this is an acceptable tradeoff for deep-submicron CMOS technology. In addition, a (111) surface is much more flexible.

While the (111) surface is easier to cleve, the mobility of the holes is about 80% higher. This makes it easier to create deep-submicron MOS devices. But there are still a few drawbacks to using the (111) surface for MOS devices. The first drawback of using higher-order surface is the lower hole mobility. But this is not a deal-breaker. Both facets have the same hole mobility.

The 111 surface is preferred for CMOS devices because the surface mobility of holes is 80% higher. This higher mobility means that higher-order surfaces are better for deep-submicron CMOS technology. Furthermore, these higher-order surfaces can be fabricated easier and have a much higher density. The (111) surface is not widely used in CMOS technology. It is a problem because they require a lot more time and money to manufacture.

Both 100 and 111 wafers have advantages and disadvantages. Generally, the 111 surface is preferable for CMOS devices and microsystems. But it is still the only one that can be used for deep submicron technology. The (111) surface is more expensive and is not ideal for MOS technology. The (111) surface is superior for CMOS technology because it is more dense.

While (111) surfaces are better for deep-submicron CMOS technology, the (100) surface is better for deeper-submicron CMOS devices. The 111 surface is not compatible with deep-submicron CMOS, and the 100 surface is more expensive. In addition, the 111 is preferable for a wide-area CMOS device.

The surface is better for deep-submicron CMOS technology. The higher-order surface is preferred for deep-submicron CMOS devices because it allows for better atomic-level design. The 100-wafer is better for deep-submicron ICs. In general, the 111-wafer is cheaper. It has more space on both sides.

The difference in Ori between (111) and (100) wafers is a result of the crystalline structure. Higher-order surfaces have lower mobility of silicon atoms. The 111-wafer has lower surface mobility. As a result, it is more difficult to manufacture deep-submicron MOS devices. In contrast, the 100-wafer has higher hole mobility.

In MOS devices, the 100-wafers are more efficient. The 111-wafers have lower energy. The higher-order surface is better for deep-submicron CMOS technologies. The 111-wafers are better for micron-sized CMOS, but aren't they too expensive? The difference between the two is based on the dimensional requirements of the device.

A 100-wafer is a thin circular slice of a single-crystalline semiconductor. The thickness of a wafer depends on its diameter. A hundred-wafer has a thickness of 25mm, while the 111-wafer is 300mm. The difference in the two-dimensional structure of a hundred-wafer is about a half-millionth of a millimeter.

Besides being more expensive, the larger the wafer, the higher the quality. The smaller the wafer, the higher the quality. A hundred-wafer is better for production in many ways, including reliability. A hundred-wafer has more advantages than a 111-wafer does. Firstly, it can be processed faster. Secondly, it allows more die to fit on a smaller area.

Why Researchers Choose (111) Silicon Wafers

Si(111) wafers are selected when the surface crystal plane matters to a process or experiment. Common use cases include epitaxial growth, surface-science studies, scanning probe microscopy, MEMS research, anisotropic etching, and experiments comparing crystal-orientation-dependent electrical, mechanical or optical behavior.

When ordering, specify the required diameter, orientation tolerance, conductivity type, dopant, resistivity, wafer thickness, polish, crystal-growth method (CZ or FZ), and any off-axis orientation. For comparison, see our (100) silicon wafers, (110) silicon wafers, and high-resistivity silicon wafers.

(111) Oriented Silicon Wafers in Stock

Please see below for a short list of (111) silicon substrates currently shown as in stock and ready to ship, including FZ, high-resistivity, intrinsic, p-type and n-type options. If you don't see what you need then please email us your specs.

Dia (mm) Type/Dopant Type/Dopant Thck (μm) Polish Resistivity Ωcm Specs
6" n-type Si:P [111] ±0.5° 300 ±15 P/P FZ >6,000 SEMI Prime, 1Flat (57.5mm), Lifetime>1,000μs, Empak cst
6" n-type Si:P [111] ±0.5° 300 ±15 P/P FZ >6,000 SEMI Prime, 1Flat (57.5mm), Lifetime>1,000μs, Empak cst
6" Intrinsic Si:- [111] ±0.5° 750 E/E FZ >10,000 SEMI notch, TEST (defects, cannot be polished out), Empak cst
6" P/B [111-4.0°] ±0.5° 625 P/E 4-15 {7.1-8.8} SEMI Prime, 1 JEIDA Flat(47.5mm), Empak cst
6" n-type Si:P [111] ±0.5° 675 P/E 1-100 SEMI Prime, NO Flats, Empak cst
6" Intrinsic Si:- [111] ±0.5° 675 C/C FZ >10,000 SEMI notch, Empak cst
5" n-type Si:P [111] ±0.1° 200 ±15 BROKEN FZ >3,000 Broken L/L wafers, in 2 pieces
5" n-type Si:P [111] 300 ±15 P/E FZ 1,000-3,000 SEMI Prime, in hard cassettes of 8 wafers
5" n-type Si:Sb [111-3.0°] ±0.5° 625 P/E 0.015-0.020 {0.0152-0.0185} SEMI Prime, 2Flats, Empak cst
4" P/B [111] ±0.5° 400 ±15 P/E FZ >20,000 SEMI Prime, 1Flat, Empak cst, TTV<5μm, Lifetime>1,000μs
4" P/B [111] ±0.5° 397 P/E FZ 10,000-15,000 SEMI Prime, Backside ACID Etched, Empak cst
4" n-type Si:P [111] ±0.25° 675 P/E FZ 10,000-20,000 SEMI TEST (Light scratches), 1Flat, Lifetime>1,000μs, Empak cst,
4" n-type Si:P [111] ±0.5° 500 P/E FZ 10,000-15,000 SEMI Prime, 1Flat, Empak cst, TTV<5μm
4" n-type Si:P [111] ±0.5° 675 P/E FZ >7,000 SEMI, 1Flat, in Empak, Lifetime>1,600μs
4" n-type Si:P [111] ±0.5° 675 P/E FZ >7,000 SEMI TEST (Scratches, in Unsealed Empak cassette), 1Flat, Lifetime>1,600μs
4" n-type Si:P [111] ±0.5° 675 P/E FZ >7,000 SEMI, 1Flat, Lifetime>1,600μs, in Empak cassettes of 6 and 8 wafers
4" n-type Si:P [111] ±0.5° 630 P/G FZ >7,000 SEMI Prime, 1Flat, in Empak, Lifetime>1,000μs, Back-side Fine Ground
4" n-type Si:P [111] ±0.25° 675 P/E FZ 7,000-10,000 SEMI Prime, 1Flat, in Empak, Lifetime>1,000μs, Light scratches
4" n-type Si:P [111] ±0.5° 150 ±10 BROKEN FZ 5,000-10,000 Broken P/E wafers, in Empak
4" n-type Si:P [111] ±0.25° 675 P/E FZ 5,000-7,000 SEMI Prime, 1Flat, in Empak, Lifetime>1,000μs
4" n-type Si:P [111] ±0.25° 675 P/E FZ 5,000-7,000 SEMI TEST (light scratches), 1Flat, Lifetime>1,000μs, in Empak
4" n-type Si:P [111] ±0.5° 525 P/E FZ >5,000 SEMI Prime, 1Flat, Lifetime>1,000μs, Empak cst
4" n-type Si:P [111-1° towards[110]] ±0.5° 525 P/E FZ >5,000 SEMI TEST (scratches on back-side), 1Flat, Empak cst
4" n-type Si:P [111] ±0.25° 525 P/E FZ 3,000-5,000 SEMI TEST (light scratches), 1Flat, Empak cst
4" n-type Si:P [111] ±0.25° 525 P/E FZ 3,000-5,000 SEMI Prime, 1Flat, in Empak cassettes of 3, 3 & 4 wafers
4" n-type Si:P [111] ±0.5° 525 P/P FZ >3,000 SEMI Prime, 2Flats, Lifetime>1,000μs, Empak cst
4" n-type Si:P [111] ±0.5° 525 P/P FZ >3,000 SEMI Prime, 2Flats, Lifetime>1,000μs, in Empak cassettes of 5, & 10 wafers
4" n-type Si:P [111] ±0.5° 525 P/P FZ >3,000 SEMI Prime, 1Flat (32.5mm)
4" n-type Si:P [111] ±0.5° 285 ±10 P/P FZ 2,500-2,700 SEMI Prime, 2Flats, Empak cst
4" n-type Si:P [111] ±0.5° 290 ±10 P/P FZ 2,500-3,500 SEMI TEST (Surface defects), 2Flats, Empak cst
4" n-type Si:P [111] ±1° 380 P/E FZ 2,000-3,000 SEMI Prime, 1Flat, TTV<5μm, Lifetime>1,000μs, in Epak cassettes of 6 wafers
4" n-type Si:P [111] ±0.5° 525 P/E FZ 1,500-3,000 SEMI Prime, 1Flat, in Empak, Lifetime>1,100μs
4" n-type Si:P [111] ±0.5° 525 P/E FZ 430-550 SEMI Prime, 1Flat, Empak cst, TTV<7μm
4" n-type Si:P [111] ±0.5° 525 P/E FZ 430-550 SEMI Prime, 1Flat, Empak cst, TTV<7μm
4" n-type Si:P [111] ±0.5° 500 ±13 E/E FZ 6.03-7.37 SEMI, 2Flats
4" Intrinsic Si:- [111] ±0.5° 500 P/P FZ >25,000 SEMI Prime, 1Flat, Empak cst
4" Intrinsic Si:- [111] ±0.5° 300 P/E FZ 20,000-40,000 SEMI, 1Flat, TTV<5μm, Empak cst
4" Intrinsic Si:- [111] ±0.5° 500 P/E FZ >20,000 SEMI Prime, 1Flat, Empak cst, Extra 3 free non-prime wafers included with 4 prime wafers
4" Intrinsic Si:- [111] ±0.5° 450 P/P FZ >20,000 SEMI Prime, 1Flat, Empak cst
4" Intrinsic Si:- [111] ±0.5° 500 P/P FZ >10,000 SEMI Prime, 1Flat, Empak cst
4" P/B [111] 350 P/E 2-3 Prime, NO Flats, Empak cst
4" P/B [111] ±0.5° 1,000 P/E 1-10 SEMI Prime, 1Flat, in hard cassettes of 7 & 8 wafers
4" P/B [111] 1,000 P/P 1-10 SEMI Prime, 1Flat, Empak cst, Cassettes of 10 and 10 wafers
4" P/B [111] 1,000 P/P 1-10 SEMI Prime, 1Flat, Empak cst
4" P/B [111] ±0.5° 525 P/P 0.2-1.0 SEMI Prime, 1Flat, in Empak cassettes of 6, 7 & 7 wafers
4" P/B [111-4°] ±0.5° 525 P/E 0.01-0.02 SEMI Prime, 1Flat, Empak cst
4" P/B [111-4°] ±0.5° 525 ±15 P/EOx 0.005-0.015 {0.0086-0.0135} SEMI Prime, 1Flat, Empak cst, TTV<5μm, 5,000A LTO on back-side
4" P/B [111-3°] ±0.5° 525 P/E 0.002-0.016 SEMI Prime, 1Flat, in Empak cassettes of 4, 5 & 5 wafers
4" P/B [111-3°] 525 P/E 0.002-0.004 SEMI Prime, 1Flat, Empak cst
4" ShowShoppingCartTally(); P/B [111] ±0.5° 1,000 P/E <0.01 SEMI Prime, 1Flat, Empak cst

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