MEMS Sensor IC Design and Fabrication
A MEMS project manager needed a quote for the following.
I am a MEMS project manager of IC Design Research and Education Center (ICDREC),. We are doing projects on MEMS sensors Fabrication and we need to buy materials from your company (please see the attached file).
Could you please give us a quotation and delivery cost so that we can order your product. We are looking forward to hear from you soon.
Reference #11910 for specs and pricing.
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How Do You Become a IC Designer?
Let’s break it down into what you need to get into IC design, depending on where you’re coming from. Whether you're a student, transitioning engineer, or just curious, here’s a step-by-step roadmap.
🎯 Step 1: Choose Your Path
There are several specializations in IC design. Start by identifying which track suits you best:
Track |
Best For |
Core Skills |
🔢 Digital IC Design |
EE, CS majors |
RTL (Verilog/VHDL), Logic design |
⚡ Analog IC Design |
EE, Physics |
Transistor theory, SPICE, layout |
🎛️ Mixed-Signal Design |
EE |
Combines analog + digital |
🧱 Physical Design |
CS/EE |
VLSI, layout tools |
✅ Verification |
CS-heavy |
Testbenches, SystemVerilog/UVM |
🧪 DFT/Test |
EE |
Scan chains, test coverage |
🛠️ EDA Tools |
CS, Math |
Programming, algorithms |
🧑🎓 Step 2: Educational Requirements
🛠️ Step 3: Learn the Core Skills
Here’s what you need to study, broken down by track:
🔢 Digital IC Design
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Verilog / VHDL
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Digital logic (flip-flops, FSMs, pipelining)
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Computer architecture (basic CPU/GPU design)
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Synthesis & Timing (setup/hold time, STA)
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Tools to learn:
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Synopsys Design Compiler
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Cadence Genus
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ModelSim / VCS
⚡ Analog IC Design
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MOSFET/BJT circuit design
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Operational amplifiers
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Matching, noise, layout techniques
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SPICE simulations
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Tools:
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Cadence Virtuoso
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Spectre / HSPICE
🧱 Physical Design
✅ Verification
🧪 Design for Test (DFT)
🛠️ EDA Tool Development
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Programming: C++, Python, Tcl
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Algorithms: Graph theory, SAT solvers, logic optimization
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Linux tools & scripting
💻 Step 4: Get Hands-On Experience
You can’t learn IC design without actual tool use or projects.
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University labs/projects: If you're in school, use your labs wisely.
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Online courses: Platforms like:
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Open-source tools to try at home:
📄 Step 5: Build a Resume/Portfolio
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Do projects: RTL design, simulation, layout, etc.
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Use GitHub to show your work.
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Do an internship or contribute to open-source (Google’s OpenROAD, for example).
🚪 Step 6: Apply to Jobs or Internships
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Big players: Intel, AMD, Nvidia, Qualcomm, Broadcom, Apple, Synopsys, Cadence, etc.
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Startups: Chiplet and AI ASIC startups are booming.
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Foundries & fabs: TSMC, GlobalFoundries, SkyWater.
Job Titles to search for:
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“RTL Design Engineer”
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“Digital Design Engineer”
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“Analog IC Design Engineer”
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“Physical Design Engineer”
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“Verification Engineer”
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“DFT Engineer”
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“EDA Software Engineer”
What is IC Design?
Integrated Circuit (IC) design is the process of creating microelectronic circuits—essentially the "brains" inside electronic devices—on a semiconductor substrate, usually silicon. This includes everything from designing the logic of a microprocessor to laying out analog circuits for amplifiers or sensors.
🧠 What is IC Design?
IC design involves conceptualizing, simulating, verifying, and laying out the microscopic components of a chip such as:
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Transistors
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Capacitors
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Resistors
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Interconnects (wiring)
These components are fabricated together on a single piece of semiconductor material, forming what's called an integrated circuit.
👷♂️ Key Job Titles in IC Design
Here’s a breakdown of common job roles in the field:
1. Digital IC Design Engineer
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Focus: Design of digital logic circuits (e.g., CPUs, GPUs, ASICs).
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Tools: Verilog/VHDL, SystemVerilog, RTL design, synthesis tools like Synopsys or Cadence.
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Tasks: Design of logic blocks, clock gating, power optimization, verification support.
2. Analog IC Design Engineer
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Focus: Circuits handling real-world signals (e.g., amplifiers, ADCs, DACs, PLLs).
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Tools: SPICE simulation, Cadence Virtuoso.
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Tasks: Transistor-level design, layout, matching, and noise/power optimization.
3. Mixed-Signal IC Designer
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Focus: Combines analog and digital (e.g., data converters, RF front ends).
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Tasks: Interface circuits, analog-digital boundary design.
4. Physical Design Engineer
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Focus: Back-end design – placing and routing the chip layout.
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Tools: Cadence Innovus, Synopsys ICC2.
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Tasks: Floorplanning, placement, routing, timing closure, power planning.
5. Verification Engineer
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Focus: Ensures chip designs work as intended before fabrication.
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Tools: SystemVerilog, UVM, formal verification tools.
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Tasks: Create testbenches, simulate and debug RTL designs.
6. DFT (Design for Test) Engineer
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Focus: Insert and verify test structures like scan chains and BIST (built-in self-test).
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Tools: Tessent (Mentor), Synopsys DFT Compiler.
7. Packaging Engineer
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Focus: Physical encapsulation and I/O design of chips.
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Tasks: Wire bonding, flip-chip design, thermal/electrical modeling.
8. EDA Tool Developer
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Focus: Develop software tools used by all the above engineers.
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Background: Strong CS/math skills; may work at Cadence, Synopsys, or Mentor.
🧪 What Substrates Are Used?
The substrate is the base material where all the devices are built. Here's what’s common:
🏭 IC Design Process: Overview
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Specification – What the chip is supposed to do.
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Architecture – Block-level design.
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RTL Design – Logic description (mostly digital).
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Simulation & Verification – Ensure correctness.
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Synthesis & Layout – Transform design into geometry.
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DFT Insertion
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Tape-out – Final design sent to fabrication.
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Fabrication – Made at a foundry (e.g., TSMC, Intel).
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Testing – Wafer probe, packaging, final test.
Integrated Circuit Design Work Flow
Here is a detailed look at the IC design flow—from an idea in someone’s head to a chip running in your smartphone. It’s a mix of engineering, science, and art, really.
🛠️ Step-by-Step IC Design Flow
1. Specification Phase
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Goal: Define what the chip will do.
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Inputs: Market needs, product goals, power, area, and performance targets.
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Output: A written spec detailing features (e.g., "A 32-bit RISC-V core with 1GHz clock speed, <1W power").
2. Architecture Design
3. RTL Design (Register Transfer Level)
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Tools: Verilog, VHDL
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Goal: Code the chip logic at a high abstraction.
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Example:
verilog
always @(posedge clk) begin if (reset) counter <= 0; else counter <= counter + 1; end
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Engineers: Digital Design Engineers
4. Functional Verification
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Goal: Make sure the RTL does what it’s supposed to.
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Tools: SystemVerilog, UVM, Questa, VCS
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Methods: Simulation, testbenches, assertions, coverage
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Bonus: Formal verification (mathematical proof of correctness)
5. Synthesis
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Goal: Convert RTL to gate-level (real logic gates)
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Tools: Synopsys Design Compiler, Cadence Genus
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Output: Netlist (standard cells mapped to a tech library)
6. Place and Route (Physical Design)
7. Timing Analysis & Optimization
8. DFT (Design for Test)
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Goal: Insert test structures to allow chip testing after fab
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Tools: Mentor Tessent, Synopsys DFT Compiler
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Includes: Scan chains, BIST, boundary scan
9. Tape-out
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Goal: Create the final files (GDSII or OASIS) sent to a foundry like TSMC, Intel, or GlobalFoundries.
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This is the big milestone before fabrication.
10. Fabrication
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Substrate Used: Usually silicon wafers, sometimes SOI or GaAs.
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Process: Optical lithography, ion implantation, etching, CMP, etc.
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Output: Bare silicon dies on a wafer.
11. Packaging and Testing
🚀 After All That… It Ships!
Now your design becomes part of:
🧑💼 Who Does What Again?
Phase |
Engineer Type |
Spec & Arch |
Systems Architect |
RTL & Logic |
Digital Design Engineer |
Verification |
Verification Engineer |
Synthesis |
Logic/Front-End Engineer |
Layout |
Physical Design Engineer |
Test Design |
DFT Engineer |
EDA Tools |
EDA Software Engineer |
Analog |
Analog IC Designer |
Packaging |
Packaging Engineer |
Product Test |
Product/Test Engineer |