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We need a special silicon wafer. Would you please kindly check as follows and advise if you could quote to this? Flatness 0.1nm Millimeter scale.
If 2 inches is difficult for you, she can also accept 1 inch.
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The flatness specifications required for a silicon wafer depend on the application, the technology node (minimum feature size), and the specific manufacturing process involved. As technology nodes have become smaller and more advanced, the requirements for wafer flatness have become more stringent.
There are several parameters used to define silicon wafer flatness specifications, including Total Thickness Variation (TTV), Site Flatness (SF), Local Flatness (LF), and Global Flatness (GF).
For example, for older technology nodes with larger feature sizes (such as 180 nm and above), the flatness requirements might not be as strict. However, for modern technology nodes (e.g., 7 nm, 5 nm, and beyond), the wafer flatness requirements are extremely tight, often demanding variations of only a few nanometers.
To provide an idea of the flatness specifications, here are some rough guidelines for different technology nodes:
Please note that these are rough guidelines, and the actual specifications may vary depending on the manufacturer's requirements and specific process conditions. It's essential to consult the manufacturer's guidelines and the needs of your particular application to determine the appropriate flatness specifications for your silicon wafers.
TIR, or Total Indicator Reading, is a term used in metrology to describe the total deviation or variation of a surface from a reference plane or ideal flatness. TIR flatness is commonly used to measure the flatness of mechanical components, such as machine beds, bearings, or other precision-engineered parts.
TIR flatness is determined by placing a part on a reference surface (such as a granite surface plate) and measuring the deviation of the part's surface from the reference plane using a dial indicator or a similar measuring device. The TIR value is the sum of the highest and lowest deviations recorded during the measurement. It represents the maximum distance between the highest and lowest points on the surface of the part.
In the context of silicon wafers, TIR flatness is not the most commonly used term. Instead, parameters such as Total Thickness Variation (TTV), Site Flatness (SF), Local Flatness (LF), and Global Flatness (GF) are more relevant for characterizing wafer flatness. These parameters help ensure that silicon wafers are suitable for high-precision processes like photolithography, which is critical for semiconductor device manufacturing.
Silicon wafer flatness refers to the degree of smoothness, uniformity, and absence of surface irregularities on 
a silicon wafer. Silicon wafers are thin slices of single crystal silicon used as a substrate material in the semiconductor industry for manufacturing integrated circuits, solar cells, and various other electronic and photonic devices.
Flatness is a critical parameter because it impacts the quality, performance, and yield of the devices fabricated on the wafer. Highly flat wafers are essential for achieving precise lithographic patterning and uniform deposition of thin films during the manufacturing process. If the wafer is not flat, it can lead to defects in the fabricated devices, such as misalignments, uneven feature sizes, and poor electrical performance.
Silicon wafer flatness is typically measured in several ways, including:
Manufacturers employ various polishing, grinding, and metrology techniques to achieve and maintain the desired flatness specifications for silicon wafers.
Below are just some ultra-flat Si Wafers
| Item | Type/Dop | Ori. | Dia (mm) | Thck (μm) | Pol | Res Ωcm | Specs |
| 6971 | n-type Si:P | [100-25° towards[110]] ±1° | 6" | 675 | P/P | 1-100 | SEMI notch Prime, Empak cst, TTV<1μm |
| S5594 | P/B | [100] | 5" | 990 ±8 | P/P | 1--25 | SEMI Prime, Empak cst, TTV<1μm |
| S5597 | n-type Si:Sb | [100] ±1° | 5" | 1,200 ±10 | P/E | 0.001-0.025 | SEMI Prime, SEMI notch, TTV<1μm Empak cst |
| F709 | n-type Si:P | [100] | 5" | 762 ±12 | P/P | May-35 | SEMI Prime, 1Flat, Empak cst, TTV<1μm, Bow<5μm, Warp<10μm |
| S6284 | n-type Si:P | [100] ±1° | 4" | 200 ±10 | P/P | FZ >1,000 | SEMI Prime, 1Flat, TTV<1μm, in Empak cst |
| C310 | Intrinsic Si:- | [100] | 4" | 510 ±5 | P/P | FZ >20,000 | SEMI Prime, 1Flat, TTV<1μm, Empak cst |
| G706 | Intrinsic Si:- | [100] | 4" | 500 | P/P | FZ >20,000 | SEMI Prime, 1Flat, TTV<1μm, Empak cst |
| 6356 | Intrinsic Si:- | [100] | 4" | 500 | P/P | FZ >20,000 | SEMI Prime, 1Flat, TTV<1μm, Empak cst |
| J302 | P/B | [100] | 4" | 600 | P/P | 1-10 | SEMI Prime, 1Flat, TTV<μm, Empak cst |
| 6570 | n-type Si:P | [100] | 4" | 400 | P/P | 1-10 | SEMI Prime, 2Flats, TTV<1μm, With lasermark, Empak cst |
| 4975 | n-type Si:Sb | [211] ±0.5° | 4" | 1,500 ±15 | P/P | 0.01-0.02 | SEMI Prime, 1Flat, Empak cst, TTV<1μm |
| L302 | P/B | [100] | 4" | 625 | P/P | 1-50 | SEMI Prime, 1Flat,TTV<1μm, Empak cst |
| J066 | n-type Si:P | [100] | 4" | 500 | P/P | 1-100 | SEMI Prime, 2Flats, TTV<1μm, With Lasermark, Empak cst |
| 4154 | P/B | [110] ±0.5° | 3" | 360 | P/P | 1-10 | SEMI Prime, 2Flats, TTV<1μm, 1-2 weeks ARO o repolish |
| 6710 | P/B | [100] | 3" | 375 | P/P | 1-20 | SEMI Prime, 2Flats, Empak cst, TTV<1μm |
| 6826 | P/B | [100] | 3" | 475 | P/P | 1-50 | SEMI Prime, 2Flats, Empak cst, TTV<0.3μm |
| D750 | P/B | [100] | 3" | 420 | P/P | <1 | SEMI Prime, 2Flats, Empak cst, TTV<1μm |
| S5580 | n-type Si:P | [100] ±1° | 3" | 2,286 ±13 | P/P | 15-28 | SEMI Prime, 1Flat, TTV<1μm, Sealed in individual csts, in groups of 5 wafers |
| S5824 | n-type Si:P | [100] ±1° | 3" | 300 ±10 | P/P | 5-10 | SEMI Prime, TTV<1μm, Empak cst |
| 6400 | n-type Si:P | [100] | 3" | 350 | P/P | 1-25 | SEMI Prime, 1Flat, TTV<1μm, Empak cst |
| 6818 | n-type Si:P | [100] | 3" | 381 | P/P | 1-30 | SEMI Prime, 2Flats, Empak cst, TTV<1μm |
| H988 | P/B | [100] | 3" | 580 | P/P | 1-100 | SEMI Prime, 1Flat, TTV<1μm, Lasermark, Empak cst |
| H714 | n-type Si:P | [100] | 3" | 350 | P/P | 1-25 | SEMI Prime, 1Flat, TTV<1μm, Empak cst |
Photolithography is a key process in semiconductor manufacturing that involves transferring intricate patterns of circuitry onto a silicon wafer. This is done by using light to project an image of the pattern onto a photosensitive material (photoresist) that has been coated on the surface of the wafer. The need for flat silicon wafers in photolithography arises due to the following reasons:
Focus accuracy: In photolithography, a high degree of accuracy is required to ensure that the pattern is precisely focused on the photoresist-coated wafer. A non-flat wafer can result in a pattern that is out of focus in some areas, leading to inconsistent feature dimensions and ultimately, non-functional devices or lower yields.
Resolution: The resolution of the photolithography process is directly related to the flatness of the wafer. If the wafer surface is not flat, it can cause inconsistencies in the exposure, leading to blurred or distorted patterns. This affects the overall quality and performance of the resulting devices.
Alignment: Photolithography typically involves multiple layers of patterning and deposition to create complex structures. Each layer must be accurately aligned with respect to the others. A non-flat wafer can cause misalignments between layers, compromising device performance and reliability.
Step height and depth of focus: In modern photolithography, particularly when using advanced techniques like deep ultraviolet (DUV) or extreme ultraviolet (EUV) lithography, the depth of focus (the tolerance for focus variation) is very shallow. Even slight wafer non-flatness can result in significant focus errors, affecting the exposure and development of the photoresist.
Process repeatability: High flatness is essential for maintaining process repeatability across multiple wafers and manufacturing runs. Any variations in wafer flatness can lead to inconsistent results and affect the overall yield and performance of the devices.
In summary, flat silicon wafers are crucial for the photolithography process to achieve high resolution, precise alignment, accurate focus, and consistent results. Maintaining wafer flatness ensures the production of high-quality, reliable, and high-performance semiconductor devices.
One of the most important process of making a microchip is the Photolithography process. The flatter the silicon substrate the better for Photolithography.
Flatness is the linear thickness variation across the the polished surface of the wafer, or a specific area of the wafer.
We have wafer's with a Total Thickness Variation (TTV) of less than 1 micron.
Silicon wafers are a key component in semiconductor devices and integrated circuits. Their dimensions and surface quality must be controlled to ensure a successful chip fabrication process.
The ideal shape of a silicon wafer is a flat disk of uniform thickness with the edges rounded to the desired profile. However, due to deformations and variations in thickness, these wafers do not always match this perfect shape.
Bow is the concavity or deformation of the silicon wafer measured from the center independent of any thickness variation. This can be a positive or negative value.
Bowing is typically a problem that is created in microfabrication processing on the working surface of a semiconductor wafer during fabrication. These processes can include depositing material, removing material, implanting dopants, annealing, baking, and so on. These process steps can create internal stresses 502 which can cause bowing of the silicon wafer.
This can lead to a variety of overlay errors, and thus the need for flatness improvement techniques. This is typically accomplished by modifying the stress on the backside of the substrate during backside processing.
The correction of the stress on the backside can be achieved by applying one or more alternating layers of different materials to the substrate. The type of material to be deposited can depend on the measured wafer bow and other device parameters (e.g., depth of memory array).
Various tools and/or modules are used to perform these techniques, and can be on a common platform or can be configured to individually move a given substrate. These modules can be configured to measure the wafer bow and/or deposit a film on the backside of the substrate based on the measured wafer bow.
An alternative technique involves using an automated substrate handling system to transport a given wafer among the various modules. The automated substrate handling system can be configured to flip or rotate the substrate as needed by the various modules.
Another technique can involve a diamond scribe being used to make a nick in the major flat of the wafer and then applying pressure to the nick in order to cleave it. This can be a great way to remove the major flat of a wafer, especially if the crystal orientation is 111> and the nicked site is along the 110> plane (which is a cleave plane).
These methods can be applied to a wide range of semiconductor devices to reduce wafer bow, resulting in increased overlay accuracy. They can be applied to many different types of silicon substrates, including 3C-SiC and Si heteroepitaxy.
During slicing, etching and lapping, a wafer often suffers from various surface characteristics such as thickness variations, warp, saw marks and kerf loss. These characteristics can affect the quality of the resulting product, as well as the cost and time needed for subsequent device production.
One way to reduce the number of undesirable characteristics of a wafer is to measure its flatness. This can be done by using noncontact capacitive scanners that are capable of measuring the thickness profile and shape of a rotating wafer at high speed.
The resulting data can then be analyzed to determine whether or not a wafer is within the spec ranges, which allows the wafer to continue being used in lithography systems, or the wafer may be reclaimed by melting it back down and turned into new ingots if it is too far out of spec.
Another method of determining the flatness of a wafer is to use a laser displacement sensor that is designed to detect the changes in the surface topography of a wafer during slicing, etching and polishing. The laser sensor is positioned on the front side of a wafer, and uses triangulation principles to measure the lateral changes in the surface of the wafer.
The measured changes in the surface topography of a chucked wafer are caused by the vacuum chuck nonplanarity and surface structures, as well as by the variation in the underlying thickness of the wafer (TTV). A SEMI-approved definition for surface flatness is SFSR or SFSD, which should be selected based on the type of lithography tool being used.
Total thickness variation (TTV) is a key parameter to measure the flatness of silicon wafers. TTV is the difference between the maximum and minimum values of thickness encountered during a scan pattern or a series of point measurements. The smaller the TTV, the more uniform the thickness of the wafer.
This is particularly important for semiconductor devices. Typically, the TTV of a silicon wafer should be below 50 nm to ensure that it does not warp and that its surface meets specifications for the lithography process used.
TTV is measured by comparing the front and back surface of a wafer between corresponding points at a specific distance. It is also used as a quality indicator for the packaging of the wafer, determining the overall surface quality.
Several researchers have focused on the theory and method of wafer backside grinding and the TTV control principle. Sun et al. [11,12] established a simulation model to analyze the wafer TTV shape and determined the two main feature components. They also conducted some grinding experiments to understand the TTV formation mechanism.
However, the underlying TTV control mechanism was not clearly revealed by their work. Moreover, they adopted the spindle configuration which might cause the “cross talking” effect between the two TTV feature components. In addition, the adjusting accuracy demand of TTV was not clearly revealed in their study.
Therefore, a precise TTV control strategy was required to improve the wafer thickness uniformity. In order to achieve this, a concise spindle posture adjustment operation was developed.
Based on the layout scheme illustrated in Figure 3b, a mathematical model for ground wafer surface shape was established to reveal the TTV control principle. In this model, the influence of adjustment angles and on wafer TTV is quantified. It can be applied to grinding tool design and processing parameter optimization to realize a good wafer thickness uniformity.
Unlike previous research, this study reveals that both and can impact with the linear superposition. This reveals a new formation mechanism of TTV shape and provides a new insight into the fine control to the TTV optimization. The proposed TTV control strategy can be applied to high-end grinding tools and advanced thinning processes to enhance wafer thickness uniformity.
Silicon wafer flatness is an important quality metric for semiconductor device fabrication. It can have a significant impact on several processes and product yield. Ideally, the wafer is a perfectly round and flat disk of uniform thickness. However, there are a variety of reasons why a wafer can deviate from this ideal shape.
Typical interferometry measurement techniques use small size optics to perform many measurements that are stitched together into a flatness map. The entire full size 300 mm wafer would be too expensive and bulky to image in one view, so these interferometry systems usually only provide flatness data for small parts of the wafer.
Surface flatness is an important lithographic process criterion because modern optical lithography tools use vacuum chucks to chuck wafers and then focus control to follow the front surface topography of the chucked wafer during exposure. Although focusing control and the smaller size of exposure slit in step-and-scan tools minimize the impact of chucked wafer non-flat topography, achieving high throughput and critical dimension uniformity (CDU) at sub-wavelength line widths requires continuous improvement in incoming wafer flatness.
A standard metric for determining the accuracy of flatness measurement has been developed and is used widely in industry. The SFQR (Site flatness-Frontside-least squares reference plane) and SFSD (Frontside-Scanner slit leveling/focus-Range/Deviation) metrics are defined in SEMI M1-1016.
These metrics should be used in conjunction with other lithographic flatness criteria such as global flatness, edge flatness, and surface thickness variation to predict the suitability of a wafer for a specific design rule node. They are not intended to be a substitute for other quality metric standards, and should be selected according to the type of lithography tool being used.
In this paper, a new system has been developed that uses a heterodyne interferometer to measure flatness with an accuracy of sub-nanometer order for 300 and 450 mm wafers. This system has been demonstrated to have repeatability of SFQR, ESFQR and GBIR over a wide range of floor vibration levels (5 Gal).
A comprehensive model-based analysis is presented that explains the distributional form and numeric relationships of several key lithographic flatness quality metrics for silicon wafers. This allows a lithographic flatness modeling framework to be created which can provide guidance for specification of silicon wafer Flatness for ULSI IC products.