How Are Silicon Wafers Classified?
Researchers can specify a silicon wafer by its conductivity type, dopant, resistivity, crystal orientation, growth method, thickness and surface finish. Start with the electrical properties your device needs, then select the physical wafer specifications that fit your process.
Request Silicon Wafers by Specification
For a quote, include p-type, n-type or undoped; preferred dopant and resistivity in Ω·cm; diameter, thickness and tolerance; (100), (110) or (111) orientation; CZ or FZ growth; polish; grade; and quantity. If you are unsure which combination fits your device, describe the fabrication steps and operating requirements.
Get your silicon wafer quote FAST! Or buy silicon wafers online and start researching today.
P-Type, N-Type and Undoped Silicon
P-type silicon wafers use acceptor dopants such as boron (B), and sometimes gallium (Ga). Holes are the majority charge carriers. N-type silicon wafers use donor dopants such as phosphorus (P), arsenic (As) or antimony (Sb), making electrons the majority carriers. The letters p and n describe the dominant carrier type; they do not mean that the entire wafer has a net positive or negative charge.
Undoped or nominally intrinsic silicon is selected when intentional doping must be minimized, often for high resistivity research. Ask for a measured resistivity range rather than assuming that every wafer labeled “undoped” has the same electrical properties. See the silicon resistivity guide for how resistivity relates to dopant concentration.
Common Silicon Dopants
| Dopant | Type | Typical role |
|---|---|---|
| Boron (B) | P-type | Acceptor; common choice for p-type substrates |
| Gallium (Ga) | P-type | Alternative acceptor for selected applications |
| Phosphorus (P) | N-type | Donor; common choice for n-type substrates |
| Arsenic (As) | N-type | Donor used where specified by the process |
| Antimony (Sb) | N-type | Alternative donor dopant |
Bulk wafer type describes the starting substrate. Later diffusion or ion implantation can form regions with a different dopant or concentration. A p–n junction is made by adjoining p-type and n-type regions; it is not a separate growth type for the whole wafer.
Other Types of Silicon Wafers
Dopant is only one way to describe a substrate. The following distinctions affect crystal purity, device layers, processing and handling.
CZ vs. FZ Silicon Wafers
Czochralski (CZ) silicon is grown from a molten silicon charge in a quartz crucible and is widely available in standard wafer specifications. Float-zone (FZ) silicon wafers are grown without that crucible and are often selected when low oxygen content or very high resistivity is important. Specify the required electrical and impurity limits; neither growth method alone guarantees suitability for a given device.
Bulk Silicon, Epitaxial Silicon and SOI
A bulk wafer is a slice of a silicon crystal. Silicon epitaxial wafers add a crystalline silicon layer on a substrate, allowing the layer and substrate to have different electrical specifications. Silicon-on-insulator (SOI) wafers have a silicon device layer separated from a silicon handle wafer by a buried insulating layer. The layer thicknesses and material properties should match the process.
Single-Side vs. Double-Side Polish
Single-side-polished (SSP) wafers have one polished face. Double-side-polished (DSP) silicon wafers have both faces polished and may be useful for alignment, wafer bonding, optics or processing from both sides. If flatness matters, specify total thickness variation (TTV), bow and warp separately from polish.
Orientation, Thickness and Grade
Crystal orientation such as (100), (110) or (111) affects processes including anisotropic etching. Wafer thickness standards help compare typical dimensions, while prime-grade silicon wafers may be appropriate when tight surface and defect requirements matter. Check the actual specification sheet before choosing a wafer solely by its grade name.
Which Wafer Type Fits Your Application?
- Electrical devices: Begin with the required bulk conductivity type, dopant and resistivity; choose an epitaxial layer or SOI structure if the device design requires one.
- MEMS fabrication: Consider orientation, mechanical behavior, surface finish, TTV and compatibility with the etching process.
- Solar cell research: Define the target cell architecture, carrier lifetime, resistivity, wafer thickness and surface preparation.
- Optical or sensor research: Consider high-resistivity FZ silicon, DSP finish or SOI when the design calls for those properties.
Explore the broader silicon wafer inventory or submit the specifications at left for a research or custom wafer quote.
Silicon Wafer Type FAQs
What is the difference between p-type and n-type silicon?
P-type silicon has holes as its majority carriers because of acceptor doping, commonly boron. N-type silicon has electrons as its majority carriers because of donor doping, commonly phosphorus.
Are intrinsic silicon wafers the same as high-resistivity wafers?
Not necessarily. Intrinsic describes silicon without intentional dopants; high resistivity is a measured electrical property. Request the specified resistivity and dopant information for the actual wafer.
Does double-side polishing change the wafer’s conductivity type?
No. Surface polish and electrical doping are separate specifications. A wafer can be p-type, n-type or undoped and still be double-side polished.
Related Silicon Wafer Guides
- Czochralski (CZ) Silicon Wafers — Explore CZ crystal growth, wafer options, and silicon ingots.
- P-Type vs. N-Type Silicon — Compare carriers, common dopants, and how each type is used.
- Silicon Wafer Doping Techniques — Learn how diffusion and ion implantation create doped regions.
- Silicon Wafer Resistivity — Understand the electrical specification to include with a dopant request.
- Highly Doped Silicon Wafers — Explore low-resistivity substrate options.
- Float-Zone Silicon Wafers — Review FZ material for high-resistivity and low-oxygen requirements.
- Silicon-on-Insulator Wafers — See when a device layer over buried oxide fits the design.